Origin of the low-frequency noise in n-channel FinFETs C.G. Theodorou a,c,⇑ , N. Fasarakis a , T. Hoffman b , T. Chiarella b , G. Ghibaudo c , C.A. Dimitriadis a a Aristotle University of Thessaloniki, Department of Physics, 54124 Thessaloniki, Greece b IMEC, Kapeldreef 75, 3001 Heverlee, Belgium c IMEP-LAHC Laboratory, MINATEC, Louis Néel, 38054 Grenoble Cedex 9, France article info Article history: Received 22 October 2012 Received in revised form 28 December 2012 Accepted 9 January 2013 Available online 28 February 2013 The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: FinFETs Generation–recombination noise Low-frequency noise Origin of noise abstract The origin of the low-frequency noise is investigated in n-channel fin-shaped field-effect transistors (Fin- FETs) in terms of the channel length and fin width. In long-channel and wide fin devices, the spectra are dominated by 1/f noise due to carrier number fluctuation, correlated with mobility fluctuations. In long- channel and narrow fin devices, the spectra are composed of both 1/f and excess generation–recombina- tion (g–r) noise components. Analysis of the g–r noise parameters lead to the conclusion that the g–r noise originates from traps in the sidewall gate oxides and in a depletion region near the sidewall inter- faces. In short-channel devices, the spectra show 1/f behavior in the weak inversion described by carrier number fluctuations and g–r noise component in the low drain current region, possibly originating from the source and drain contacts process. Ó 2013 Elsevier Ltd. All rights reserved. 1. Introduction Tri-gate (TG) fin-shaped field-effect transistors (FinFETs) are promising device structures for sub-100-nm scaling of MOSFETs due to their immunity to short-channel effects (SCEs) [1–3]. However, as the FinFETs scale down, the low-frequency (LF) noise becomes more pronounced due to its inverse dependence with the gate area, and it could lead to serious limitations of the analog and digital circuits functionality [4,5]. In addition, the LF noise is a non- destructive and sensitive diagnostic tool to characterize the traps present at the gate oxide/silicon interface and in the depletion layer of silicon [7–14]. Therefore, it is important to clarify the ori- gin of the LF noise in nanoscale TG FinFETs, in order to optimize their noise level. In most cases of n-channel TG FinFETs, the origin of the LF noise has been investigated in long-channel devices [6–13], and recently, the investigation was extended to gate lengths down to 60 nm [12,13]. In several cases, it was found that the noise spectra contain two noise sources: 1/f noise ascribed to carrier number fluctua- tions (CNFs) due to carrier exchange between the gate dielectric traps near the interface and the channel and generation–recombi- nation (g–r) noise components due to charge traps in the gate oxide or in the silicon depletion region. Analysis of the g–r noise components at different temperatures enabled the extraction of the trap characteristic parameters (energy level, capture cross- section) [12,13]. In the weak inversion region of n-channel FinFETs, in some cases, the mobility fluctuation was found to be the domi- nant 1/f noise generation mechanism [14]. Recently, the LF noise in the linear region from weak to strong inversion has been investi- gated in p-channel FinFETs, with channel length ranging from 70 nm to 1 lm [15]. It has been shown that in p-channel FinFETs, the LF noise is composed of both 1/f noise governed by CNF and g–r noise originating from traps in the gate oxide [15]. In this work, we investigate systematically the impact of the fin width on the LF noise of n-channel TG FinFETs with long-channel length (L =1 lm) and short-channel length (L = 25 nm). It is shown that the LF noise spectra are composed both of 1/f noise and g–r noise components. The origin of the 1/f and g–r noise components is clarified in the long-channel and short-channel devices in terms of the fin width. 2. Experimental The n-channel FinFETs were fabricated at IMEC (Leuven, Bel- gium) on silicon on insulator (SOI) wafers with 145 nm buried oxide thickness. The device parameters are channel doping con- centration 10 15 cm 3 , TiN/HfO 2 gate insulator stack with equiva- lent gate oxide thickness t ox = 1.7 nm, constant fin height H fin = 65 nm, fin width W fin varying from 5 nm to 1 lm, and chan- nel length L = 25 nm and 1 lm. The investigated devices have five fins, and the effective device width is 5  (2H fin + W fin ). Details for the device fabrication processes are presented elsewhere [16]. 0038-1101/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2013.01.009 ⇑ Corresponding author at: IMEP-LAHC Laboratory, MINATEC, Louis Néel, 38054 Grenoble Cedex 9, France. Tel.: +33 616116148. E-mail address: cgtheodo@auth.gr (C.G. Theodorou). Solid-State Electronics 82 (2013) 21–24 Contents lists available at SciVerse ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse