Low frequency noise statistical characterization of 14nm FDSOI technology node E. G. Ioannidis 1,2 , C. G. Theodorou 1 , S. Haendler 2 , M.-K. Joo 1,4 , E. Josse 2 , C. A. Dimitriadis 3 and G. Ghibaudo 1 1 IMEP-LAHC, INPG, Minatec, BP 257, 38016 Grenoble, France 2 STMicroelectronics, 850, rue J. Monnet, BP 16, 38921 Crolles, France 3 Dpt of Physics, Aristotle University of Thessaloniki, 54124, Greece 4 School of Electrical Engineering, Korea University, 136-701, Seoul, South Korea Abstract— In this paper, we performed a statistical analysis of the low-frequency noise (LFN) in 14nm FDSOI n-MOS devices. Front and back gate interfaces were characterized, revealing an equal contribution to the total noise level. Finally, the LFN variability is analyzed and a comparison to previous CMOS technologies is presented. Keywords—Low-frequency Noise; characterization; CMOS; I. INTRODUCTION A significant improvement in terms of threshold voltage variability and short channel effects (SCEs) in highly scaled CMOS can be achieved using ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology, while maintaining compatibility with standard planar CMOS technology [1-2]. However, the silicon film and buried oxide thickness reduction can cause strong noise coupling effects between the front and back interfaces [3-4]. Furthermore, the oxide area shrinking in advanced technology devices not only leads to a significant threshold voltage mismatch increase [5] but can also cause a drain current noise variability enhancement [6]. The latter has been proven to be related to the random telegraph noise (RTN) which appears in small-area MOSFETs [7]. In FDSOI MOSFETs, it has been well established that the total drain current flicker (1/f-like) noise originates from carrier number fluctuations (CNF) due to carrier trapping/detrapping into gate dielectric traps at both interfaces (channel/gate oxide and channel/buried oxide) which may also induce correlated mobility fluctuations (CMF) [3-4]. In this work, a 2-interface CNF model approach is used to extract the two interfaces trap density values. In addition, a statistical analysis of the LFN is performed in order to study the drain current noise variability in 14nm FDSOI technology node. Finally, a noise variability comparison between 14nm FDSOI, 28nm FDSOI and 20nm Bulk technology nodes is presented. II. MEASURED DEVICES AND EXPERIMENTAL SET-UP Drain current noise measurements were performed on n- MOS transistors issued from 14nm FD-SOI CMOS technology [8], operating in linear regime (V d = 50mV). The measured devices channel length is the minimum (L = 20 nm), while the widths (W) are lying in the range of 0.06-3 m. Time domain drain current sampling measurements were performed under constant biasing, with Agilent B1500/1530 Semiconductor Device Analyzer [9], followed by a Fast Fourier Transform to obtain the current noise spectra. Using three different sampling rates and the same total number of samples, we managed to cover the noise spectrum frequency bandwidth from 0.5 up to 500×10 3 Hz and increase its resolution. III. INTERFACE CHARACTERIZATION Figs 1-2 display drain current power spectral density measurements of front (V b = 0V) and back (V g = 0V) gate operation modes, respectively, for W = 1 m and L = 80 nm. The spectra are averaged over 15 dies, giving a clear 1/f-like frequency dependence in all bias conditions. The extracted values of the normalized drain current noise SI d /I d 2 at f = 1 Hz for both front (FG) and back-gate (BG) Fig. 2. Drain current noise SId versus frequency for back-gate mode and various back gate voltages (15 dies averaging). Fig. 1. Drain current noise SId versus frequency for front-gate mode and various gate voltages (15 dies averaging). EUROSOI-ULIS 2015 978-1-4799-6911-1/15/$31.00 ©2015 IEEE 181