Fast Rescheduling of Multi-Rate Systems for HW/SW Partitioning Algorithms B. Knerr, M. Holzer, and M. Rupp * Vienna University of Technology Institute for Communications and RF Engineering Gusshausstr. 25/389, 1040 Vienna, Austria {bknerr, mholzer, mrupp}@nt.tuwien.ac.at Abstract In modern designs for heterogeneous systems with their extreme requirements on power consumption, execution time, silicon area and time-to-market, the HW/SW partition- ing problem belongs to the most challenging ones. Usually its formulation, based on task or process graphs with com- plex communication models, is intractable. Moreover most partitioning problems embed another NP-hard problem in its core: a huge number of valid schedules exist for a single partitioning solution. Powerful heuristics for the partition- ing problem rely on list scheduling techniques to solve this scheduling problem. This paper is based on a rescheduling algorithm that performs better than popular list scheduling techniques and still preserves linear complexity by reusing former schedules. A sophisticated communication model is introduced and the rescheduling algorithm is modified to serve multi-core architectures with linear runtime. Keywords: Task Scheduling, HW/SW Partitioning, Multi-Rate Systems, Fast Rescheduling, Multi-Core Plat- forms 1 Introduction Modern system design, especially in the wireless do- main, has to face hard challenges with respect to chip area, power consumption, and execution time while time-to- market is critical. The diversity of the requirements has lead to extremely heterogeneous system architectures, whereas the short design cycles boosted the demand for early design decisions, such as architecture selection and HW/SW par- titioning on the highest abstraction level, i.e. the algorith- mic description of the system. HW/SW partitioning can in general be described as the mapping of the interconnected functional objects that constitute the behavioural model of the system onto a chosen architecture model. The task of partitioning has been thoroughly researched and enhanced * This work has been funded by the Christian Doppler Laboratory for Design Methodology of Signal Processing Algorithms. during the last 15 years and produced a number of feasible solutions, which depend heavily on their prerequisites: the architecture model, the communication model, the granu- larity of the functional objects, etc. A short overview of the most relevant work in this field is given in the following section. In most HW/SW partitioning approaches heuristics are used to traverse the search space, see Sec. 2. The embed- ded scheduling problem is always solved by list scheduling algorithms and/or estimations about the expected system runtime. In our earlier work we have shown that a better scheduling technique can be incorporated in many HW/SW partitioning algorithms permitting more reliable results of the partitioning process [11]. This work enriches the pro- posed rescheduling technique with a more realistic commu- nication model and provides the extension to multi-core ar- chitectures. The rest of the paper is organised as follows: after the related work section the common system abstraction into SDF graphs is briefly introduced. Afterwards the HW plat- form model, which the system should be mapped on, is de- scribed. Sec. 5 discusses the complexity that partitioning engines have to deal with. In Sec. 6 the fundamental idea of the proposed rescheduling algorithm and the extension to multi-core platforms are presented. In Sec. 7 results, ob- tained by its application to typical task graph sets, are pre- sented. Sec. 8 concludes the paper. 2 Related Work Heuristic approaches dominate the field of partitioning algorithms, since partitioning is known to be an NP-hard problem in most formulations [1]. Genetic algorithms [14] have been extensively used as well as simulated anneal- ing [7]. To a smaller degree tabu search [3] and greedy al- gorithms [5] have also been applied. Other research groups developed custom heuristics such as the GCLP algorithm in [10] or the early work in [6]. Formulations of the inherent multi-processor scheduling problem have been shown to be NP-complete [4, 12]. The Copyright 2005 IEEE. Published in the Proceedings of the 39th Annual Asilomar Conference on Signals, Systems, and Computers, Oct 30 to Nov 2, 2005, Pacific Grove, CA, USA. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE.