Circuit Fabrication at 17 nm Half-Pitch by Nanoimprint Lithography Gun-Young Jung, ²,‡ Ezekiel Johnston-Halperin, § Wei Wu, ² Zhaoning Yu, ² Shih-Yuan Wang, ² William M. Tong, ², | Zhiyong Li, ² Jonathan E. Green, § Bonnie A. Sheriff, § Akram Boukai, § Yuri Bunimovich, § James R. Heath, § and R. Stanley Williams* ,² Hewlett-Packard Laboratories, 1501 Page Mill Road, Palo Alto, California 94304, DiVision of Chemistry and Chemical Engineering, California Institute of Technology, Pasadena, California 91125, and AdVanced Materials & Processes Labs, Technology DeVelopment Operations, Hewlett-Packard Company, 1000 Circle BouleVard, CorVallis, Oregon 97330 Received October 26, 2005; Revised Manuscript Received January 6, 2006 ABSTRACT High density metal cross bars at 17 nm half-pitch were fabricated by nanoimprint lithography. Utilizing the superlattice nanowire pattern transfer technique, a 300-layer GaAs/AlGaAs superlattice was employed to produce an array of 150 Si nanowires (15 nm wide at 34 nm pitch) as an imprinting mold. A successful reproduction of the Si nanowire pattern was demonstrated. Furthermore, a cross-bar platinum nanowire array with a cell density of approximately 100 Gbit/cm 2 was fabricated by two consecutive imprinting processes. The cross-bar architecture has been adopted by many as a leading candidate architecture for post-CMOS nanoelectronic circuits 1 because of its scalability down to the molecular scale, addressability of each cross point cell with a demul- tiplexer, its reconfigurability to tolerate defects in the circuit, 2 and its manufacturability at a reasonable cost with nanoim- print lithography. 3,4 We have previously demonstrated an 8 × 8 nanoscale electronic circuit using molecules as functional elements in the junction of the metal cross bar fabricated by nanoimprint lithography at 65 nm half-pitch (hp). 5 Since then, we have successively scaled the nanoimprint process down to 50 nm 6 and further to 30 nm hp 7 by using molds that were fabricated using electron beam lithography (EBL). However, severe proximity effects on neighboring features during e-beam exposure has made it extremely challenging to produce molds with dense wires smaller than 30 nm hp at the present time. 8 Our need for patterning metal nanowires with 17 nm hp drove us to seek alternatives to EBL for mold fabrication. One solution was to perform a spatial frequency-doubling process on an existing e-beam generated mold. 9 An alterna- tive approach was to use a mold patterned by the superlattice nanowire pattern transfer (SNAP) method, which could create high aspect ratio arrays of metal 10 or semiconductor 11 nanowires at dimensions down to 8 nm hp from the selectively etched edges of the superlattice. In this Letter, we report on the combination of the SNAP patterning method with the nanoimprinting replication method to fabricate metal nanowire arrays and cross-bar circuits at a feature half-pitch (hp) of 17 nm. This approach should enable high throughput manufacturing of ultra-high-density metal and semiconductor nanowire circuits for memory, 12 logic, 2,13 sensing, 14 opto- electronic, 15 and other applications. 16 Features in a superlattice structure with a less than 15 nm hp have been previously patterned on a polymer resist by nanoimprint lithography. 17 However, transferring such pat- terns from the imprinted resist to the substrate as metal wires is far more difficult and until now has not been reported. Imprinting ultradense patterns poses several additional chal- lenges. For example, issues such as the thickness of the imprinting resist, resist adhesion to the mold features, composition of the resist material and the selectivity of various etching processes, etc., all require higher levels of control than are needed for less demanding replication tasks. In this paper, we will briefly review the procedure for fabricating a silicon mold with features at 17 nm hp from a superlattice and focus on describing a UV-based imprinting process for replicating the 17 nm hp pattern from the silicon mold to metal wires on a glass substrate. The silicon molds used in this study were fabricated with the previously reported SNAP techniques 10,11 with a slight * Corresponding author: e-mail, stan.williams@hp.com; phone, (+1)- 650-857-6586; fax, (+1)650-236-9885. ² Hewlett-Packard Laboratories. ‡ Current address: Department of Materials Science and Engineering, Gwangju Institute of Science and Technology (GIST), Gwangju, Republic of Korea. § Division of Chemistry and Chemical Engineering, California Institute of Technology. | Advanced Materials & Processes Labs, Technology Development Operations, Hewlett-Packard Co. NANO LETTERS 2006 Vol. 6, No. 3 351-354 10.1021/nl052110f CCC: $33.50 © 2006 American Chemical Society Published on Web 02/04/2006