Techniques for wirebond free interconnection of piezoelectric ultrasound arrays operating above 50 MHz A.L. Bernassau 1 , D. Flynn 2 , F. Amalou 2 , M.P.Y. Desmulliez 2 , S. Cochran 1 1 Institute for Medical Science and Technology, University of Dundee, Dundee, UK 2 Microsystems Engineering Centre, School of Engineering and Physical Sciences, Heriot-Watt University, Edinburgh, UK a.bernassau@elec.gla.ac.uk Abstract — Interconnects between high frequency ultrasound (HFUS) arrays and external circuitry may be difficult and expensive because of the small element pitch, as low as 15 m, and the large number of piezoelectric elements, up to 256. The wire bonding commonly used can be time consuming and difficult to achieve on piezocomposite material because of the relatively soft filler material. Moreover, the minimum pitch is limited by the footprint requirement for the bonding head. This requires the creation of an electrical fan-out, in turn increasing the size of the array package; this interconnect technology is disadvantageous for medical applications such as ophthalmology and dermatology. This paper proposes a wirebond free bonding process for HFUS piezocomposite arrays operating at frequencies above 30 MHz. The suggested process is integration of ultrasound "chips" with a silicon (Si) wafer using state-of-the-art fabrication techniques and materials including anisotropic conductive film, through silicon vias, powder blasting and laser machining. Keywords: Micromachining, integrated electronics, high- frequency ultrasound, ultrasonic arrays. I. INTRODUCTION High frequency ultrasound (HFUS) transducer arrays, operating above 30 MHz, are needed to improve high- resolution medical imaging in areas such as dermatology and ophthalmology to allow electronic scanning and improve the image quality compared to the single-element transducers and early arrays now commercially available. However, several fabrication problems remain to be resolved fully. One of these is the interconnect between the transducer and the electronic component, which can be difficult because the element pitch for a high frequency array is very small and the number of elements can be large, for example, 256 for a linear array and 128 for a linear phased array. A common interconnect method used in HFUS arrays is wire bonding [1]. This method can be time consuming but also difficult to achieve on composite as the wires do not bond properly on epoxy adhesive material. Furthermore the pitch size of the contact pad cannot be smaller than a few tens of μm as the head of the wire bonder cannot be smaller than this. This necessitates the creation of an electrical fan out for frequencies above 30 MHz. The creation of the fan out increases the footprint of the array, which can be an issue for medical applications such as ophthalmology or small animal imaging where the overall physical size of the probe is important. This paper focuses on wire bond free interconnection for high frequency piezoelectric ultrasound arrays above 30 MHz. This process involves the use of anisotropic conductive film (ACF) and through silicon via (TSV) technologies. These two techniques have been intensively studied over the past few years as solutions for high density interconnect, low temperature bonding for flat panel displays, and semiconductors packaging applications [2]. II. OUTLINE OF FABRICATION PROCESS The fabrication process involves the bonding of a piezoelectric substrate that is patterned with fine array electrodes to a Si wafer. This wafer may incorporate electronic circuits (integrated circuits) and signal processing devices in the future. Gold (Au) bumps are grown by electroplating on the Si wafer only. The bonding is achieved by ACF. The Au pillars compress and squeeze the ACF and interconnects are obtained which are conductive in the Z-axis only, between the Si and the array elements. The alignment is achieved and pressure and heat are applied with flip-chip bonding equipment. TSVs and the area cut out for filling the backing layer are achieved by laser machining and powder blasting, respectively. Connections from back to front of the Si wafer have been achieved to date by bonding in place fine wire with conductive adhesive. Electroplating should replace this technique in the future. III. PROOF OF CONCEPT FABRICATION A. Piezocomposite A piezocomposite was patterned by lift-off photolithography [3]. This composite had piezoceramic features in the shape of partial annuli and epoxy filler compatible with conventional photolithography processing [4]; it was used only to demonstrate the concept of the interconnect process and the shape of the ceramic features does not affect the proof of concept of the fabrication. The lift-off photolithography process has been fully described elsewhere [3]. After lift-off, the Cr-Au electrodes and lower photoresist layer (PMGI) with a height of 0.7 μm were left on the substrate. Fig. 1(a) shows a high magnification photomicrograph of the 50 MHz array pattern on the piezocomposite. Fig. 1(b) is a photograph taken at lower magnification, showing the marks at the edge of the samples that have been placed there to align the silicon array die by flip-chip bonding. Furthermore, the pattern design includes pads for electroplating bumps. In the investigation reported here, bumps were not grown on the piezocomposite substrate but only on the Si wafer. This removes a step in the fabrication process and also avoids the need to manipulate the fragile piezocomposite in the electroplating bath. This work was financially supported by the UK Engineering and Physical Research Council (EPSRC) 10.1109/ULTSYM.2009.0276