Power-Aware Wrappers for Transaction-Level Virtual Prototypes: a Black Box Based Approach Ons Mbarek, Alain Pegatoquet, Michel Auguin Houssem Eddine Fathallah Abstract—Low power design and verification at the Electronic System Level (ESL) have recently emerged as a challenging research field. This work 1 presents a reliable solution to add such capabilities to Transaction-Level virtual prototypes composed of black-box hardware Intellectual Properties (IPs). This solution relies on a wrapper-based approach in which power intent specification and verification are added as separate layers of the IPs functional ones. Using Synopsys’s Innovator TM virtual prototyping toolset, our approach has been validated with an audio application TL platform. Results show our approach benefits to enable different power intent alternatives exploration with low simulation speed overhead and reduced modeling effort. Keywords-Intellectual Properties (IPs), low power design and verification, virtual prototyping (VP), Transaction Level Models (TLM), Power Domain (PD), power intent, System-on-Chip (SoC), Design-by-Contract (DbC), Unified Power Format (UPF) standard. I. INTRODUCTION & RELATED WORK One of the key Electronic System Level (ESL) design methodologies is Transaction-Level virtual prototyping (VP) solutions. These solutions such as the Synopsys Innovator TM tool [1], the Mentor Graphics Vista TM solution [2] or the Imperas Open Virtual Platforms (OVP TM ) environment [3], rely on building software models of embedded systems through assembling SystemC Transaction-Level (TL) [4] Intellectual Property (IP) cores. Depending on the used virtual prototyping tool, these cores can be either white-box IPs with accessible source codes or black-box ones already pre-designed, pre-compiled and pre-verified. For instance, unlike OVP TM which provides an open source library composed of white-box IP models, an Innovator TM VP is usually composed of black-box IPs taken from the Synopsys DesignWare System-Level Library (DWSLL) [5]. Power-aware TL virtual prototyping have recently gained great interest. At this level, rapid exploration of architecture design alternatives can be made. So, greatest and costless power reduction can be achieved. On the one side, EDA vendors, industrials and academics have supplied tools and methodologies that ease system- level power modeling, analysis and optimization. Most of 1 This work is supported by the French National Research Agency (ANR) project HELP bearing reference ANR-09-SEGI-006 them focus on enabling power estimation and analysis inside existing VP tools using annotation-based approaches [6] [7]. Authors in [8] [9] [10] [11] have proposed approaches for source code instrumentation targeting only white-box types of IPs. So far, validation of efficient and well-structured power management strategies according to a specific low power design has not been targeted by state of the art approaches and existing VP tools. This is due to the lack of system-level power intent specification support [12]. Power intent refers to the design’s power domains partitions, supply network distribution, retention strategies and system power modes. Among additional common shortcomings of these mentioned ad hoc approaches are the lack of modularity and the clear separation of power and functional concerns. On the other side, some EDA tool vendors have come up with automation solutions for low power design, verification and exploration. Most of these solutions [14] [15] are built on support for the recent IEEE-1801 TM Unified Power Format (UPF) industry-standard [13]. This standard enables power intent specification and verification along the design flow from Register Transfer Level (RTL) to signoff. In our previous work [16], we have proposed a methodology to add power intent and management features to Transaction-Level functional models based on abstract UPF standard concepts and check relevant power-aware properties. An efficient approach to instrument white-box TL IPs with these capabilities according to this methodology has been also proposed. However, this approach cannot be applied to black-box TL IPs due to some modeling constraints. An approach to handle the particular case of black-box IPs while applying the same methodology is hence required. The work shown in this paper contributes to define a modular approach that applies our methodology to add low power design, management and verification features to TL platforms composed of black-box IPs. In this approach, the IEEE 1801 (UPF) standard [13] has been used as a support. Separation of power and functional concerns is achieved by wrapping power-aware features on top of black-box IPs. In the sequel, section 2 briefly describes the main goals and stages of our power-aware TL design methodology. Section 3 introduces some constraints to apply this methodology on black-box types of virtual platforms. Section 4 explains our wrapper-based approach. In the fifth LEAT, University of Nice Sophia Antipolis-CNRS Bâtiment Forum, Campus Sophia@Tech 930-Route des Colles, Sophia Antipolis 06903, France. {mbarek, pegatoquet, auguin}@unice.fr LEAT, University of Nice Sophia Antipolis-CNRS Bâtiment Forum, Campus Sophia@Tech 930-Route des Colles, Sophia Antipolis 06903, France. {fathallah}@etu.unice.fr