Perturb and Simplify: Optimizing Circuits with External Don’t Cares Shih-Chieh Chang Malgorzata Marek-Sadowska Synopsys Inc. Electrical and Computer Engineering Department, University of California at Santa Barbara Abstract zyxwvut Earlier optimization techniques based on Automatic Test Pattern Generation [3], [4], and [7] could not handle external don’t cares. We propose a technique that uses external don’t cares during the ATPG guided logic opti- mization. This technique transforms external don’t cares into intemal don’t cares. Thus, the optimization can uti- lize the external don’t cares to obtain better results. Additionally, we also discuss some perturbation tech- niques to improve further results of logic optimizers. Based on a careful analysis of don’t cares migration dur- ing incremental changes of an optimized circuit, we have developed a strategy to guide optimization.We have per- formed experiments on MCNC and ISCAS benchmarks and the results are very encouraging. 1 Introduction External don’t cares are primary input combinations for which primary outputs are of no interest. These don’t cares may originate from designers’ specifications or be caused by the unreachable states of sequential circuits. Recent automated test pattem generation (ATPG) based logic optimizers [3] [4] [7] have proven very successful both in reducing circuit size and run-time memory usage. Since external don’t cares can be very useful for logic optimization, we propose an approach that uses external don’t cares during the ATPG guided logic optimization. The ATPG based techniques [3] [4] [7] iteratively add redundant wires(gates) to remove other wires(gates) in a circuit. A crucial procedure in these techniques is to per- form wire redundancy checking. A wire is redundant if a test pattern does not exist for a stuck-at fault test at this wire. On the other hand, the presence of extemal don’t cares has the effect that some irredundant wires (without considering external don’t cares) may become redundant. For example, in Fig la, the wire zyxwvutsr g3->g5 (bold in the fig- ure) is not redundant because there exist test patterns I(a,b,c,d)=(O,O,O,l), (l,O,O,l), (l,O,O,l)l for g3->g5 stuck- at-1 test. However, if the circuit has extemal don’t cares c*d, the wire zyxwvutsrq g3->g5 is redundant. This is because all test patterns are contained in the external don’t cares c,d. Therefore, the wire g3->g5 can be removed together with the gates gl and zyxwvutsrqp g3. - One straightforward approach to identify whether test patterns are included in the external don’t cares is to ver- ify the set containment conditions. It can be performed using BDD based techniques. However, set operations are computationally expensive and potentially result in expo- nential complexity. Furthermore, the redundancy check- ing procedure is intensively applied in the ATPG based logic optimization techniques. Consequently, such a costly containment checking to utilize external don’t cares cannot be of practical use. In this paper, we propose a technique that can implicitly calculate the containment condition. Our idea is to build a fictitious side circuit which can implicitly determine if test patterns are con- tained in external don’t cares. By adding this fictitious side circuit to the original circuit, any wire that is redun- dant under external don’t care conditions becomes untest- able in the newly built circuit. Therefore, we can smoothly apply ATPG based techniques to optimize a combinational circuit with external don’t cares. A simple demonstration of such a fictitious circuit is shown in Fig lb (highlighted in the figure). It can be easily checked that the irredundant wire g3->g5 in Fig l a becomes untestable and is therefore redundant in Fig 1 b. In this paper, we also discuss some perturbation tech- niques to further improve logic optimization results. The purpose of such perturbations is to avoid premature termi- nation of the optimization process resulting in local mini- mum. The basic operation in our technique is to perform single-wire substitution (replace a wire by another wire) zy as discussed in [2]. This kind of single-wire substitution is very useful to alter circuit structure without additional costs. In our technique, instead of randomly applying such single-wire substitutions, we carefully guide the wire replacement procedure. It is based on an analysis of how internal don’t cares are redistributed when a wire is replaced by another wire. This paper is organized as follows. Section 2 reviews the techniques introduced in [41 [7][3]. Section 3 presents our approach of utilizing external don’t cares. In section 4, we discuss some perturbation related issues. Finally, the experimental results are shown, followed by conclu- sions. zyxwv 402 1066-1409/96 $5.00 0 1996 IEEE