LAYGEN – Automatic Analog ICs Layout Generator Nuno Lourenço, Nuno Horta Instituto de Telecomunicações, Instituto Superior Técnico, Technical University of Lisbon, Lisboa, Portugal e-mail: nlourenc@gmail.com; n.horta@ieee.org Abstract 1 — This paper describes an innovative analog IC layout generation tool based on evolutionary computation techniques. The designer provides a high level layout description. This template contains placement and routing constrains and is independent from technology. This expert knowledge is used to guide an evolutionary optimization kernel during the automatic generation of the layout for the target technology. Additionally, this template can be used hierarchically in the definition of templates for more complex circuits. The LAYGEN tool is here presented and demonstrated for the layout generation of typical circuit structures. I. INTRODUCTION As the evolution of global semiconductors market indicates a fast growth of integrated circuits with both analog and digital functionalities, the development of design automation tools has become a key factor to enhance the efficiency of integrated circuits design cycle. However, despite the development efforts, the use of design automation tools to support the analog integrated circuit design, in industrial environments, is still limited, especially when compared with the digital counterpart [1]. Therefore, the research and development of new design automation techniques and methodologies is, clearly, justified to overcome the current demands of the analog and mixed-signal integrated circuits industry. The initial approach to analog layout generation was to apply the features used for digital design [2]. However, given the differences between digital layout design and its analog counterpart, this approach presented a limited ability to generate high quality layouts. The next generation of tools followed an optimization-based approach using a small library of devices [3-4]. Within this approach, complex circuits have to be generated from the small set of devices yielding high execution times. Besides, structures like stacked transistors were not likely to be automatically generated. In 2003, Jangkrajarng et al proposed IPRAIL [5] a retargeting specific application that extracts, from an original handmade layout, a template that is used to generate the target layout. Recent approaches rely on user defined procedural module generators to create complex modules, and optimizers to perform module placement and routing, ALADIN [6] is a good example of such a platform. The methodology for automatic analog ICs layout design described in this paper is based in the introduction of a new abstraction layer between technological details and the designer guidelines. The abstract layout representation captures the designer knowledge independently of technology and allowing some specifications changes. The focus of this new design approach is improving design reusability and retargetability. The template, independence from technological details and support for moderate changes on device and modules specifications introduces an additional level of flexibility to the design. Design productivity is increased only if the target layout can be automatically generated from the template, this is LAYGEN’s purpose. In order to implement an efficient search of the solution space evolutionary computation techniques [10-11] are here applied to handle such a multi-objective multi-constrain problem. The paper is organized as follows. In section II, a general overview on typical layout generation procedures, including the proposed tool, is given. Afterwards, in section III, the LAYGEN’s template data-model is described. Then, in sections IV and V, the LAYGEN kernel for generating the placement and routing are discussed. In section VI, preliminary implementation results are presented. Finally, in section VII, the conclusions and future work are addressed. II. DESIGN APPROACH It is acknowledged that each designer/company has its own layout style but often this style is very regular. For a large number of applications, even with some specifications or technological changes, the design guidelines for most common cells like amplifiers or current sources etc. are kept the same. For simple cells, parametric generators are a valid solution to implement these guidelines. However, though technological detail may also be included as parameters, these module generators are highly dependent of technology making them difficult to reuse. In addition, for complex cells the development of effective parametric generators has proven ineffective, either on design-time or design- reusability. In order to cope with these limitations, our approach stores these design regularities in a layout meta-description that is independent of technology. The template, together with LAYGEN and a set parametric module generators at device- level, provide the designer with a technological and specification independent way of for defining some of the most commonly used cells. This paper addresses the automation of this newly introduced abstraction level; nevertheless the complete automatic design flow incorporating this new feature is the final target of the ongoing work. The complete automatic design flow is shown in Figure 1.