Architecture and FPGA Implementation of LTE PSS and SSS Synchronizer Jason Kurniawan * , Nur Ahmadi † , Trio Adiono ‡ Department of Electrical Engineering, School of Electrical Engineering and Informatics Bandung Institute of Technology, Jl. Ganesha No. 10 Bandung, 40132, Indonesia Email: * jasonkurniawan93@gmail.com, † nurahmadi@stei.itb.ac.id, ‡ tadiono@stei.itb.ac.id Abstract—This paper presents an architecture of the LTE signal receiver system to acquire the physical cell identity (PCI). The PCI plays an important role to determine other reference signals, which are further used in channel estimation, cell selection/reselection, and handover procedures. The information required to determine the PCI is carried by two LTE syn- chronization signals: Primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS). This paper describes an architecture of PSS and SSS Synchronizer Blocks for LTE-FDD 4G Baseband Receiver System. The synthesis results using Altera Quartus software show that the proposed design of each block consumes 5895 logic gates with the maximum frequency of 114.97 MHz for PSS Synchronizer block and 1332 logic gates with the maximum frequency of 375.09 MHz for SSS Synchronizer block. Both designs have been successfully implemented and verified on Altera DE4 FPGA board. Index Terms—Physical Cell Identity LTE, Synchronization Signals, PSS, SSS, FPGA I. I NTRODUCTION Nowadays, communication between humans become more essential in daily life. The development of industrial technol- ogy in general could not be separated with the need of com- munication. The close relation between industrial technology and communication technology had given some contributions to trigger and accelerate some new ideas for faster and reliable communication technology. One of the most popular communication technologies is Long Term Evolution (LTE), which is a highly flexible radio interface developed by 3GPP (3rd Generation Partnership Project) [1]. In the LTE system, synchronization signals play an im- portant role to acquire the physical cell identity (PCI) or NCellID which can be further used in channel estimation, cell selection/reselection, and handover procedures. There are two sinchronization signals which are Primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS). These two signals for the case of LTE-FDD (channel band- width 10 MHz, FFT Size 1024, and sampling frequency 15.36 MHz) will be our main interest in this paper as can be seen in Figure 1 (blue-colored box). The input signals for the PSS & SSS Synchronizer blocks are assumed to be already in the frequency domain (baseband signal). The main objective in this paper is acquire the information of physical cell identity (PCI) whose value will be updated on each symbol processed. For the transmitter, there is already a standarized method by 3GPP to generate the synchronization signals for each RF A/D Timing Synchronizer CP Remover RF Equalizer & Channel Coding PSS & SSS Synchronizer Demodulator Data Out Fig. 1. LTE 4G baseband receiver system specific PCI number by using certain mathematical equations. However, for the receiver, it will only receive the sets of numbers without knowing whether those are PSS, SSS, other reference signals, or data. The method or algorithm used to determine the PCI value of one data stream input can be various depending on the designer of the receiver. Basically, the idea is the same, which is the reverse of the SSS generation method. However, how the circuit design is made will be unique one with another. In this paper, we propose architectures for PSS and SSS Synchronizer which are implemented in Verilog HDL. The ref- erence model is written in MATLAB for verification purpose. The functional simulation and the synthesis are performed by using Modelsim tool and Altera Quartus software, respectively. The performance of our proposed designs is evaluated based on two metrics, which are the area consumption (resource utilization) and the maximum frequency. II. LITERATURE REVIEW A. Synchronization Signals in LTE System The information of physical cell identity (PCI) is carried by syncronization signals which are PSS and SSS. PSS carries the information about NCellID 2 (physical layer ID) while SSS carries the information about NCellID 1 (cell group ID). There are 3 variations of NCellID 2 value, which are [0, 1, 2], while NCellID 1 has 168 variations which are [0 ··· 167]. Therefore, there are 504 variations of value of PCI (3*168 = 504). From the value of NCellID 1 and NCellID 2, the value of PCI can be determined as follows PCI = (3 * NCellID 1 )+ NCellID 2 (1) According to LTE standards [2], in the Frequency Domain Duplex (FDD), PSS is located at the seventh symbol of each half-frame and the SSS is located at the sixth symbol. Their positions on the frame structure is illustrated in Figure 2.