International Review of Electrical Engineering (I.R.E.E.), Vol. 5, N. 2 March-April 2010 Manuscript received and revised March 2010, accepted April 2010 Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved 803 A 1.2V High Band-Width Analog Multiplier in 0.18µm CMOS Technology Amir Ebrahimi 1 , Hossein Miar Naimi 2 Abstract ｱ Analog multiplier is an important building block for many analog computational applications. In this paper, a new compact, low power structure and low voltage CMOS analog multiplier is proposed. The proposed structure incorporates a cross-coupled squarer circuit. The most important features of this topology are low power consumption and high band-width that makes it suitable for use in high frequency applications. All of these are implemented using a compact circuit. The circuit is designed and analyzed in 0.18µm CMOS process model and the key features like bandwidth and THD are extracted. Simulation results for the circuit with a 1.2V single supply show a very low power consumption and better band-width with respect to comparable structures. Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved. Keywords: CMOS Analog Multiplier, Four Quadrant, Cross-Coupled Squarer Circuit Nomenclature B Input DC bias voltage. C OX MOS gate oxide capacitance per unit area. C DBn Drain-to-bulk capacitor in NMOS transistors. C GDn Gate-to-drain capacitor in NMOS transistors. C GSn Gate-to-source capacitor in NMOS transistors. C SBn Source-to-bulk capacitor in NMOS transistors. C DBp Drain-to-bulk capacitor in PMOS transistors. C GSp Gate-to-source capacitor in PMOS transistors. K Trans-conductance parameter of MOS transistor. K n NMOS trans-conductance parameter. K P PMOS trans-conductance parameter. L Channel length of MOS transistor. R sx(n) NMOS velocity saturation resistor. R sx(p) PMOS velocity saturation resistor. V DD Supply voltage. V GS MOS gate-to-source voltage. V SB MOS source-to-bulk voltage. V t MOS threshold voltage. V T0 MOS threshold voltage in zero bias condition. V Tn NMOS threshold voltage. V TP PMOS threshold voltage. W MOS channel width. MOS body effect coefficient. , Mismatch terms for threshold voltage of transistors. MOS velocity saturation parameter. (10 -7 /tox)V -1 I. Introduction Todays by the advances in communication and signal processing systems, power consumption, power supply and bandwidth become critical problems in circuit design. Analog multipliers are important building blocks for analog signal processing applications such as modulation, oscillators, phase frequency detection, fuzzy integrated systems[1]-[9].The multiplier performs a linear product of continuous signals x and y yielding an output z Kxy in which K is a constant with suitable dimension[1]. Different structures for optimizing different features have been proposed for analog multipliers. Some of these features are: operating speed, power consumption, supply voltage, bandwidth and etc. As we know, there are many tradeoffs between different performance features; enhancing one degrades some others. The previous topologies for multipliers have different approaches in implementation. One of these approaches is using transistors in triode region [1], [8]. The circuit of [1] suffers from nonlinearity. The main drawback of [8] is the large number of transistors in the implemented circuit. The dominant approach is using transistors in saturation especially for wideband applications [3]. As another classification, multipliers may be implemented in current mode or voltage mode. In [4] a current mode multiplier is proposed for high speed applications in which for each multiplicand, say x, the circuit needs an additional input of 2x. Building precise 2x is not always possible, so this makes the circuit more complicated and inserts additional error. In [3] and [5] two voltage mode multipliers are proposed and as a drawback both need two different power supply. Using flipped voltage followers, some proposed circuits minimized the power supply [3], [7].