Compact, Low-Voltage, Low-Power and High- Bandwidth CMOS Four-Quadrant Analog Multiplier Amir Ebrahimi Integrated Circuits Research Lab (ICRL) Babol University of Technology Babol, Iran a.ebrahimi@stu.nit.ac.ir Hossein Miar Naimi Department of Electrical Engineering Babol University of Technology Babol, Iran h_miare@nit.ac.ir Mohammad Gholami Department of Electrical Engineering Sharif University of Technology Tehran, Iran mgh_elec@yahoo.com Abstract— In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18µm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25µw quiescent power with 2GHz band- width and 1.5% THD. Keywords-analog multiplier; four-qudrant; high-bandwidth low power; low voltage I. INTRODUCTION Today the advances in communication and signal processing systems increase the need for the building blocks with lower power consumption, lower power supply and higher bandwidth. Analog multipliers are important building blocks for many analog signal processing applications such as modulation, adaptive filters, phase frequency detection, fuzzy integrated systems[1]-[9].The multiplier performs a linear product of continuous signals x and y yielding an output z Kxy = , where K is a constant with suitable dimension. Varieties of multipliers have been designed for different optimization objectives [1]-[10]. Some of these objectives are: operating speed, power consumption, supply voltage, bandwidth and etc. The previous topologies for multipliers have different approaches in implementation. For example, in [4] a current mode multiplier is proposed for high speed applications in which for each multiplicand, say x, the circuit needs an additional input of 2x. Building precise 2x is not always possible. So, this makes the circuit more complicated and inserts additional error. In [3] and [5] two voltage mode multipliers are proposed that the drawback of them is the need for two different power supply. One of the good features of our proposed topology is its simplicity and compact structure. Furthermore, it is designed with single low voltage supply. We will analyze this topology in next sections. The rest of this paper is organized as follows. Section II explains the design trend and structure of the multiplier. Section III is about the characteristics and performance analysis of the multiplier. Simulation results are presented in section IV and finally section V gives the conclusions. II. DESIGN TREND In the proposed circuit, all of the transistors operate in saturation region. As known, the behavior of MOS transistor in this region can be described as 2 ( ) D GS t I KV V = - (1) Where, I D is the drain current, V GS is gate-to-source voltage, t V is the threshold voltage, K=µC OX W/2L is the trans- conductance parameter, L and W are the length and width of the transistor channel and µ is the carrier mobility. A. Sub-Circuit Consider the circuit in Fig. 1.a. In this stacked structure, I O can be calculated from the following equations. O Dn Dp I I I = = (2) GSn V B Y A = + - (3) GSp V A X = - (4) Consequently, I Dn and I Dp can be written as 2 ( ) Dn n Tn I K B Y A V = + - - (5) 2 ( ) Dp P TP I K A X V = - - (6) From (5), (6) and (2) we have 2 2 ( ) ( ) P TP n Tn K A X V K B Y A V - - = + - - (7) Equation (7) concludes (8) and (9). ( ) ( ) P TP n Tn K A X V K B Y A V - - = + - - (8) ( ) ( ) n Tn P TP n P K B Y V K X V A K K + - + + = + (9) 2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD) 978-1-4244-6817-1/10/$26.00 ©2010 IEEE