IJIRST –International Journal for Innovative Research in Science & Technology| Volume 2 | Issue 02 | July 2015 ISSN (online): 2349-6010 All rights reserved by www.ijirst.org 87 Design and Synthesis of 16 bit Adaptive Digital Filter Architecture Nishi Gupta Rakesh Joon Stduent Associate Professor Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering GITAM, Kablana, Jhajjar, Haryana GITAM, Kablana, Jhajjar, Haryana Ruby Garg Stduent Department of Electronics and Communication Engineering GITAM, Kablana, Jhajjar, Haryana Abstract Filtering data in real-time requires dedicated hardware to meet demanding time requirements. If the statistics of the signal are not known, then digital filtering algorithms can be implemented to estimate the signals statistics iteratively. Modern field programmable gate arrays (FPGAs) include the resources needed to design efficient filtering structures. This research aims to combine efficient filter structures with optimized code to create a system-on-chip (SoC) solution for various digital filtering problems. LMS algorithms have been coded in VHDL. The designs are evaluated in terms of filter throughput, hardware resources, and speed performance and to evaluate the mean square error of 16 adaptive digital filters. Keywords: LMS, FPGA, VHDL, Soc _______________________________________________________________________________________________________ I. INTRODUCTION This paper is to explore the use of embedded System on Chip (SoC) solutions that modern Field Programmable Gate Arrays (FPGAs) [1] offer. Specifically, it will investigate their use in efficiently implementing digital filtering applications, [2] Different architectures for the digital filter will be compared with LMS algorithms implemented in the FPGA fabric only, to determine the optimal system architecture. and design and synthesized of 16bit LMS Adaptive Filter with and without using DA and to evaluate mean square error of 16 bit adaptive filter with parameter convergence factor 0.5 and filter length 16 bit and no of iteration 1000. Recently mobile communication systems require size reduction, high levels of integration and fewer surface-mounted devices as to achieve low cost, robust and highly efficient operation of the system. FPGA technology provides benefits of low cost and of high integration with neighboring circuits. [3] Best architecture give the better solution for system chip level. The electronics industry has achieved an excellent growth over the last few decades, mainly due to the rapid advances in integrated technologies and FPGA Technology. The use of integrated circuits in high performance computing, telecommunications, and consumer electronics has been growing at very fast pace in digital domain. Better architectures of digital filter give the best output of filtering of data.[4] The purpose of this thesis is to explore the use of embedded System on Chip (SoC) solutions that modern Field Programmable Gate Arrays (FPGAs) offer. Specifically, it will investigate their use in efficiently implementing digital filtering applications, Different architectures for the digital filter will be compared with LMS algorithms implemented in the FPGA fabric only, to determine the optimal system architecture Modern computational power has given us the ability to process Tremendous Amounts of data in real‐ time. DSP is found in a wide variety of Applications, such as: filtering, speech recognition, image enhancement, and data Compression, neural networks; as well as functions that is unpractical for Analog implementation, such as linear‐ phase filters Signals from the real World are naturally analog in form, and therefore must first be discretely Sampled for a digital computer to understand and manipulate. The signals are discretely sampled and quantized, and the data is represented in binary format so that the noise margin is overcome. This makes DSP algorithms insensitive to thermal noise. Further, DSP algorithms are Predictable and repeatable to the exact bits given the same inputs. [6]This has the advantage of easy simulation and short design time. Additionally, if a prototype is shown to function correctly, then subsequent devices will also .There are many advantages to hardware that can be reconfigured with different programming files.[7] Dedicated hardware can provide the highest processing performance, but is inflexible for changes. Reconfigurable hardware devices offer both the flexibility of computer software, and the ability to construct custom high performance computing circuits the hardware can swap out configurations based on the task at hand, effectively multiplying the amount of physical hardware available.