IJSRD - International Journal for Scientific Research & Development| Vol. 3, Issue 01, 2015 | ISSN (online): 2321-0613 All rights reserved by www.ijsrd.com 490 Design and Analysis of Different Type Single Bit Adder for ALU Application Jaswant Singh 1 Gaurav Sharma 2 1 Research Scholar M.Tech (VLSI) 2 Assistant Professor 1,2 Department of Electronics & Communication Engineering 1,2 Mewar University, Chittoragarh Abstract— In these dissertation four types of 1-bit adder has been designed and simulated using 180nm CMOS technology in tanner tool at a various supply voltage from1.0V to 1.8 V & compare their results with respect to various parameters like delay, area & power consumption. The adder is the most commonly used arithmetic block of the Central Processing Unit (CPU) and Digital Signal Processing (DSP), therefore its performance and power optimization is of utmost importance. With the technology scaling to deep sub-micron, the speed of the circuit increases rapidly. Due to continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. At the same time, the power consumption per chip also increases significantly due to the increasing density of the chip. Therefore comparison has been carried out by assuming the circuits with minimum size transistors, to minimize the power consumption. Power consumption is a function of load capacitance, frequency of operation, and supply voltage. A reduction of any one of these parameter is beneficial. A reduction in power consumption provides several benefits. Less heat is generated, which reduces problems associated with high temperature, such as the need for heat sinks. This provides the consumer with a product that costs less. Key words: Central Processing Unit (CPU), Digital Signal Processing (DSP), CMOS technology I. INTRODUCTION Rapid growth in semiconductor technology has led to shrinking of feature sizes of transistors using deep submicron (DSM) process. Modern portable battery operated devices such as cell phones, laptops; PDAs are particularly affected by this as high power dissipation reduces battery service life. The adder is the most commonly used arithmetic block of the Central Processing Unit (CPU) and Digital Signal Processing (DSP), therefore its performance and power optimization is of utmost importance. With the technology scaling to deep sub- micron, the speed of the circuit increases rapidly. At the same time, the power consumption per chip also increases significantly due to the increasing density of the chip. Therefore, in realizing modern Very Large Scale Integration (VLSI) circuits, low-power and high-speed are the two predominant factors which need to be considered. Like any other circuits' design, the design of high-performance and low-power adders can be addressed at different levels, such as architecture, logic style, layout, and the process technology. As the result, there always exists a trade-off between the design parameters such as speed, power consumption, and area. Recently, the requirement of probability and the moderate improvement in battery performance indicate power dissipation is one of the most critical design parameters day by day the demand of probability and mobility is increasing. Also the area of chip design is taken into consideration while talking about probability. Hence three most widely accepted parameters to measure the quality of a circuit or to compare various circuit styles are area, delay and power dissipation. There are three major sources of power consumption in digital CMOS circuits, which are summarized in the following equation Leakage Circuit Short Switching Total P P P P     The first term represents the switching component of power. The short circuit power dissipation is due to the direct path from short circuit currents Isc, which arises when both the NMOS and PMOS transistors are active, conducting current directly from power supply to ground. Finally, leakage current power dissipation arises from substrate injection and sub threshold effects, which is primarily determined by fabrication technology considerations. The objective of our dissertation is to design a low-power and smaller area adder and also compare its performance parameter with different types of adder architecture II. BASIC THEORY AND TYPES OF ADDER Adders are commonly used in the critical path of many building blocks of microprocessors and digital signal processing chips. Adders are critical component not only for addition, but also for subtraction, multiplication, and division. Addition is one of the fundamental arithmetic operations. A fast and accurate operation of a digital system is greatly influenced by the performance of the resident adders. The most important parameter for measuring the quality of adder designs is propagation delay, and area. Adder or summer is a digital circuit that performs addition of numbers. In modern computers adders reside in the arithmetic logic unit (ALU) where other operations are performed. Although adders can be constructed for many numerical representations, such as Binary-coded decimal or excess-3, the most common adders operate on binary numbers. A. Application of Adders:  Used in CPU side  Used in networking side  Used in DSP oriented system  In application-specific processors  In biomedical applications  In image processing and video processing.