A Scalar Interpolator/Compressor for the Improvement of Sensor Linearity Nikos Petrellis Computer Science and Engineering Dept. TEI of Thessaly 41110 Larissa, Greece npetrellis@teithessaly.gr Abstract— A hardware linear interpolator with logarithmic and exponential curve slope correction is described in this paper allowing real time linearity improvement of low resolution sensors like the miniaturized, wearable or implantable ones used for health monitoring. A compression is performed by the interpolator when the input signal is sparse or changes with low frequency. A signal distorted by the digitization process can be approximated even when its available samples are in non- uniform distances. Multiple interpolators with identical or increasing resolution can be connected in series. A three-stage interpolator with 9-bit input and 12-bit output typical resolution is implemented using 14% of the Logic Elements of an Altera Cyclone III EP3C25N Field Programmable Gate Array and is tested using an ADC developed by the author. An improvement close to 100% has been measured at the Signal to Noise and Distortion Ratio (SNDR) and at the Spurious Free Dynamic Range (SFDR) of the ADC when a 2MHz sinusoidal input was used. Keywords— Interpolation, Seonsors, Analogue/Digital Conversion, Compression, Resolution I. INTRODUCTION A large number of interpolation methods have been presented in the literature for signal reconstruction including the simpler to implement linear (or first-order hold) interpolation [1] in the time domain or more complicated interpolation schemes in the frequency domain, Lagrange, min- max interpolation, etc. The approaches that are based on the post-processing of an Analogue/Digital Converter (ADC) output include the correction of Differential or Integral Non- Linearity (DNL/INL) static errors. These methods are based on the excitation of an ADC with DC levels or voltage ramps (histograms [2] or best fit curves [3]). The histogram approach includes initially the excitation of an m-bit ADC with a ramp signal in order to get the initial 2 m outputs and then the ramp signal is shifted up to retrieve another set of 2 m outputs [4]. The differences between the corresponding values are used for the estimation of the INL/DNL error [5][6]. The DNL linearity errors can be corrected by signed error correcting factors that are stored in large look up tables. The calibration of the DNL error coefficients in real time is also described in [7]. In [8], appropriate Lagrange and min-max interpolation methods are proposed for high precision signal reconstruction, implementable with low complexity hardware. In [9] the interpolation is performed by a weighted summation of a number of preceding and succeeding samples that are available in order to estimate the current signal value. The authors of [9] compare the performance of their own algorithms (Least Mean Lattice - LSL interpolation, QR Decomposition LSL algorithm, QRD-LSL). The dynamic linearity errors that are measured by SNDR, SFDR and Total Harmonic Distortion (THD) are taken into consideration in approaches like [1] and [7]. In the first-order interpolation, two successive samples are assumed to be linearly connected. If the original analogue signal is curved between the successive samples, the first-order hold is not accurate but the error is smaller if the distance between these samples is short. However, higher order interpolation schemes like Cubic spline interpolation, may also fail to find a curve that accurately matches the input signal. The proposed interpolation method is based on a first-order interpolation in the time domain for lower complexity and is evaluated on an FPGA. Its simplicity stems from the fact that it requires only a small number of adders, counters and comparators. The error of the interpolated values in exponential or logarithmic signals (e.g., a capacitive biosensor output) is further reduced by employing additional error correcting rules. Low resolution signals like the ones generated by the wearable or implantable smart sensors with extremely small dimensions used in healthcare applications, can be significantly improved by the proposed interpolation method. Experimental results show that the SNDR of a 2MHz sinusoidal signal has been increased from 21dB to approximately 40dB (approximately 100% improvement) using a 3-stage interpolator scheme. The SFDR has been improved in this case from 27dB to 54dB. The interpolator described in this paper is tested on sinusoidal signals digitized by an ADC developed in TSCM90nm CMOS technology [10]. The interpolator can also perform real time compression in the case of sparse or signals that change with a very low frequency. For example, the output of a capacitive pressure sensor was compressed down to the 11% of its original size. A signal is represented at the interpolator output as a sequence of (V, C) pairs implying that the value V of the signal appears C times. This type of compression has been adopted by standards like LZ77/78. The proposed interpolator is scalar in the sense that higher linearity can be achieved if multiple interpolators are serially connected. The architecture of the developed interpolator is described in Section II. Experimental results are presented in Section III. This work is patent pending (provisional patent with application number 20130100627 - Greek Patent Office)