1170 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 6,JUNE 2006 TransparentDFT:ADesignforTestabilityandTest GenerationApproachforSynchronousSequentialCircuits Irith Pomeranz and Sudhakar M. Reddy Abstract—This paper describes a design for testability (DFT) approach forsynchronoussequentialcircuitsthatcombinesscanwithnonscanDFT inatransparentway.DFTcontrolinputsandscanchaininputsareusedas primaryinputsofthecircuit,andscanchainoutputsareusedasprimary outputs of the circuit during test generation to eliminate the distinction between functional clock cycles and the various types of nonfunctional clockcycles.Theresultis1)shorttestapplicationtimesduetothenonscan DFTmodesandtheabilitytouselimitedscanoperationsand2)theability todetectallthecombinationallyirredundantfaultsduetothescanmode. Index Terms—Design for testability (DFT), scan circuits, synchronous sequentialcircuits,testcompaction,testgeneration. I. I NTRODUCTION Transparent-scan was proposed in [1] as an approach to test genera- tion and test compaction for scan circuits. Under the transparent-scan approach, the distinction between scan clock cycles and clock cycles where the circuit operates in functional mode is eliminated. Test gen- eration and test compaction procedures under this approach consider the scan chain input(s) and the scan select input as primary inputs of the circuit, and the scan chain output(s) as primary output(s) of the circuit. This provides complete flexibility in interleaving scan clock cycles and functional clock cycles during test generation. It results naturally in limited scan operations, where a scan chain is shifted a number of times smaller than its length [2]–[5]. Experimental results presented in [1] show that transparent scan reduces the test application time for benchmark circuits compared to the best known earlier scan- based procedures. The transparent-scan approach was found to be necessary in [6] in order to test critical paths in a microprocessor with partial scan. Although transparent scan reduces the test application time relative to other scan-based approaches, it still relies on scan operations for controlling and observing the circuit state. Scan operations, even limited ones, take several clock cycles. Design for testability (DFT) approaches for synchronous sequential circuits that do not use scan [7]–[11] have the potential of reducing the test application time to a larger extent than scan-based approaches. The goal of the DFT approach proposed in this work is to combine the advantages of transparent scan with those of nonscan DFT approaches under an approach we refer to as transparent DFT. To introduce the transparent-DFT approach, we first show in Table I the modes of operation of a standard scan flip-flop, and in Fig. 1 a conceptual description of such a flip-flop. We denote by y i the output (the present-state variable) of flip-flop i, and by Y i the input (the next state variable) of flip-flop i in the original circuit. We assume that the circuit has n flip-flops, numbered 1, 2,...,n. For simplicity we assume that all the flip-flops are included in a single scan chain. In the Manuscript received June 30, 2004; revised January 7, 2005 and March 27, 2005. The work of I. Pomeranz was supported in part by National Sci- ence Foundation (NSF) Grant CCR-0098091 and in part by Semiconductor Research Corporation (SRC) Grant 2001-TJ-950. The work of S. M. Reddy was supported in part by NSF Grant CCR-0097905 and in part by SRC Grant 2001-TJ-949. This paper was recommended by Associate Editor S. Hellebrand. I. Pomeranz is with the School of Electrical and Computer Engineering (ECE), Purdue University, West Lafayette, IN 47907 USA. S. M. Reddy is with the Electrical and Computer Engineering (ECE) Depart- ment, University of Iowa, Iowa City, IA 52242 USA. Digital Object Identifier 10.1109/TCAD.2005.855947 TABLE I TRANSPARENT-SCAN MODES Fig. 1. Transparent-scan flip-flop. circuit with scan, the input of flip-flop i (1 ≤ i ≤ n) is denoted by ˆ Y i . For 1 <i ≤ n, ˆ Y i is a function of Y i , the scan select input s_sel, and y i-1 . For i =1, y i-1 is replaced by the scan input s_inp. We also have a scan output s_out, which is connected to y n . For the transparent-DFT approach we introduce the following changes relative to scan. Instead of the scan select input s_sel, we have DFT select inputs denoted by d_sel1,d_sel2,...,d_selM. Each combination of values on d_sel1,d_sel2,...,d_selM corre- sponds to a different mode of operation. Possible modes of operation are as follows. The normal or functional mode of operation must always be possi- ble, and we implement it corresponding to d_sel1 = d_sel2 = ... = d_selM =0. In this case, ˆ Y i = Y i for 1 ≤ i ≤ n. Scan should be included as a possible mode of operation since it guarantees the detection of every combinationally irredundant stuck- at fault when full scan is used. We implement scan for d_sel1 = d_sel2 = ... = d_selM − 1=0 and d_selM =1. In this case, ˆ Y i = y i-1 for 1 <i ≤ n and ˆ Y 1 = s_inp, where s_inp is the scan input. We also have a scan output s_out connected to y n . Other combinations of d_sel1,d_sel2,...,d_selM can be used to set ˆ Y i = Y j , ˆ Y i = Y j , ˆ Y i = y j or ˆ Y i = y j , where 1 ≤ j ≤ n. For example, with ˆ Y i = y i for 1 ≤ i ≤ n we obtain the implementation of the DFT approach called Freeze [7], where the circuit is allowed to stay in the same state while primary input vectors are applied. With ˆ Y i = y i+1 for every 1 ≤ i<n and ˆ Y n = s_inp, we obtain a scan operation in the opposite direction to the one obtained when ˆ Y i = y i-1 for 1 <i ≤ n and ˆ Y 1 = s_inp. More complex functions of Y j and y j can also be used for ˆ Y i , 1 ≤ i ≤ n. This includes the option of using a different function for every flip-flop. It is also possible to incorporate scan chain modification techniques such as the one presented in [12] and [13]. Under this technique, XOR gates are included between scan flip-flops in order to achieve power reductions. In the context of transparent DFT, this technique can be used for reducing the test application time. We describe a particular transparent-DFT implementation with two control inputs d_sel1 and d_sel2 in Section II. We give an example of a test sequence under the transparent-DFT approach in Section III. We demonstrate the effectiveness of the transparent-DFT approach rela- tive to the transparent-scan approach by performing two experiments outlined next. In both experiments, we assume the equivalent of full scan circuits, i.e., we assume that all the flip-flops are modified to incorporate DFT modes of operation. 0278-0070/$20.00 © 2006 IEEE