Full Integration of Highly Manufacturable 512Mb PRAM based on 90nm Technology J.H. Oh, J.H. Park, Y.S. Lim†, H.S. Lim†, Y.T. Oh, J.S. Kim, J.M. Shin, J.H. Park, Y.J. Song, K.C. Ryoo, D.W. Lim, S.S. Park, J.I. Kim, J.H. Kim, J. Yu, F. Yeung, C.W. Jeong, J.H. Kong, D.H. Kang, G.H. Koh, G.T. Jeong, H.S. Jeong, and Kinam Kim Advanced Technology Development and † Process Development Team, Semiconductor R&D Div., Samsung Electronics Co., Ltd. San #24, Nongseo-Ri, Kiheung-Eup, Yongin, Kyunggi-Do 449-900 Korea Tel) 82-31-209-6549, Fax) 82-31-209-3274, E-mail) ojhee.oh@samsung.com Abstract Fully functional 512Mb PRAM with 0.047µm 2 (5.8F 2 ) cell size was successfully fabricated using 90nm diode technology in which we developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge 2 Sb 2 Te 5 . The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior. The reliability of the 512Mb chip was also evaluated as a write-endurance over 1E5 cycles and a data retention time over 10 years at 85°C. Introduction Among various candidates for ideal non-volatile memory, phase-change random access memory (PRAM) has shown the most convincing prospects for commercial high density products. [1, 2] Fig. 1 shows the roadmap for PRAM development. In order to be mass-productive and cost- effective memory, it is highly required to develop high density PRAM with a cell size as small as <10F 2 in simple process flow with good scalability and sufficient sensing margin. The requirements can be satisfied by 1) developing a scalable switching device with a sufficiently high on-cell- current (Ion), 2) improving or maintaining the Ge 2 Sb 2 Te 5 (GST) transition behaviors, and 3) designing a well- optimized circuit especially for writing procedure to acquire a wide sensing window. The approaches, we have taken in this work, are the replacement of tri-gate MOSFET with a vertical diode for large Ion in a small cell, the precise control of parameters in GST module process, and the adoption of slow- quench and write-and-verify schemes. Diode scheme needs higher cell operation voltage than that of MOSFET scheme by about 1.0V, the adoption of dual gate oxide is inevitable for low external supply voltage less than 3.3V. The uniformity of Ireset can be improved by using the ring-type bottom electrode contact (BEC) scheme as described in previous work. [3] Another critical technology of self-aligned BEC (SABEC) scheme was developed for high manufacturability. The SABEC has several advantages of free-misalign margin, a reduction of critical mask layer, and a favorable correlation effect between BEC and diode. In addition, patterning the top-electrode (TE) and the GST under optimal etching condition was proved to improve the write-endurance. Key Features of 512Mb PRAM Fig. 2 is a full chip image of a fabricated 512Mb PRAM, which consists of 16 banks × 32 Mb/bank. This chip has many circuit design options with its size of 10770 × 8500µm 2 . The key device features of 512Mb PRAM are summarized in Table 1. The 512Mb PRAM is mainly featured by 5.8F 2 unit Figure 1. PRAM development roadmap with design rule and unit cell size. Figure 2. A photograph of 512Mb PRAM chip.