Error Floors of LDPC Coded BICM Aditya Ramamoorthy Department of Electrical and Computer Engineering Iowa State University Ames, Iowa 50011 Email: adityar@iastate.edu Nedeljko Varnica Marvell Semiconductor Inc. Santa Clara, CA 95054 Email: nvarnica@marvell.com Abstract— In recent years performance prediction for commu- nication systems utilizing iteratively decodable codes has been of considerable interest. There have been significant breakthroughs as far as the analysis of LDPC code ensembles is concerned but the more practical problem of predicting the FER/BER of a particular code has proved to be much more difficult. In this work we present a technique (based on the work of Richardson ‘03) for finding lower and upper bounds on the performance of LDPC coded BICM systems for a given code. The insight gained from the prediction technique is used to design interleavers that improve the error floors of these systems. I. I NTRODUCTION The performance of iterative coding schemes such as turbo codes and LDPC codes is well-known to suffer from the error floor problem. The performance curve of such codes typically consists of two different parts. In the low SNR region the frame error rate (FER)/bit error rate (BER) drop very fast with increasing SNR. This part of the curve is usually referred to as the waterfall region. However beyond a certain SNR the slope of the curve changes and the drop in FER/BER is no longer as sharp. In particular the irregular LDPC codes introduced in [1] have an error floor that is much more pronounced than regular codes [2]. For codes that are decoded using a bounded distance de- coder (e.g. RS codes) or a maximum likelihood decoder (e.g. convolutional codes) it is possible to predict the performance of the code by using the union bound on the probability of error. This bound is reasonably tight at high SNR. However for iteratively decoded codes no such clear characterization of decision boundaries exists and consequently performance prediction is much harder. It is of great interest to understand the behavior of iterative decoding and characterize its failure mechanisms especially in the error floor region. In the con- text of data storage applications this problem is of utmost importance because the frame or sector error rate of interest is typically below 10 −10 .Thus it becomes very important to have a tool for predicting the FER in the high SNR region. While there is extensive literature on the asymptotic analysis of ensembles of codes ([1] [3] [4] among others) that consider performance bounds in the limit of large block length, the more practical issue of performance analysis for a given code has been much harder. The only channel where the decoding failure has a clear characterization is the binary erasure channel (BEC). As noted by [5] the iterative decoding algorithm hits a fixed point if and only if the set of variable nodes erased by the channel forms a graphical structure called a stopping set. Thus the problem of estimating the FER of the code becomes the problem of finding the stopping set spectrum of the code. For all other channels the problem of FER prediction is much harder. In [6] Richardson presented a numerical technique for the prediction of the error floor of an LDPC code with BPSK modulation over the AWGN channel. Other approaches that we are aware of include [7] [8] and [9]. In this paper we extend Richardson’s method of error floor prediction to obtain lower and upper bounds on the frame error rate of LDPC coded bit interleaved coded modulation (BICM) [10]. Furthermore we exploit the insight gained from the prediction technique to design efficient interleavers be- tween the code and the constellation mapping to further reduce the error floors. Error floor prediction for systems using M-ary modulation and iterative codes is important in storage systems that store data in multiple levels e.g. M-ary optical storage [11] . LDPC Decoder Constellation Mapper Constellation Demapper -1 LDPC Encoder n Fig. 1. System Block Diagram The organization of the paper is as follows. Section II de- scribes our technique for performing the error floor prediction for a LDPC coded BICM system. Results that demonstrate the accuracy of the technique are also included. Section III explains the design of the interleaver based on the prediction technique that is found to have improved error floors and Section IV concludes the paper. II. ERROR FLOOR PREDICTION TECHNIQUE In this section we shall outline our strategy for estimating the error floor for LDPC coded BICM. The system under consideration is shown is Fig. 1. We consider only Gray mapping since this mapping has been found to have the best performance at medium block lengths [12]. Of course other 1-4244-0353-7/07/$25.00 ©2007 IEEE This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the ICC 2007 proceedings.