Double gate silicon on insulator transistors. A Monte Carlo study F. G amiz * , J.B. Rold an, A. Godoy, J.E. Carceller, P. Cartujo Departamento de Electr onica y Tecnolog  ıa de Computadores, Universidad de Granada, Campus Universitario, Avd. Fuentenueva s/n, 18071 Granada, Spain The review of this paper was arranged by Prof. S. Cristoloveanu Abstract Electron transport properties in double-gate-silicon-on-insulator (DGSOI) transistors are comprehensively studied. Quantum effects are analyzed by self-consistently solving the 1 D Poisson and Schroedinger equations. Once the electron distribution is known, the Bolztmann transport equation is solved by the Monte Carlo method, and the role of volume inversion is analyzed both at room and at lower temperatures. A comparison between symmetrical-gate and asymmetrical-gate configurations is also provided, showing the superior performance of symmetric devices. Finally, velocity overshoot is also studied. Monte Carlo simulations were performed to clarify the dependence of velocity overshoot effects on the low-field mobility, channel inversion charge and silicon layer thickness. We show that electron mobility is mainly determined by the increase in the phonon scattering rate as the silicon thickness is reduced, i.e., the lower the silicon thickness the lower the electron mobility, while velocity overshoot effects for ultrathin DGSOI inversion layers are dominated by the reduction of the average conduction effective mass, i.e., the lower the silicon thickness the higher the velocity overshoot peak. Ó 2004 Elsevier Ltd. All rights reserved. PACS: 73.40.Qv; 72.20.Fr; 71.70.Fk; 72.10.Fk 1. Introduction A double-gate-silicon-on-insulator (DGSOI) struc- ture consists, basically, of a silicon slab sandwiched between two oxide layers. A metal or polysilicon film is deposited on each oxide [1]. Each of these films then acts as a gate electrode (front and back gate), which is capable of generating an inversion region near the two Si–SiO 2 interfaces, if the appropriate bias is applied. Thus, two metal-oxide-semiconductor-field-effect-tran- sistors (MOSFETs) would be sharing the substrate, the source and the drain. However, the main feature of these structures arises from the concept of volume inversion, introduced and demonstrated some time ago by Balestra et al. [2,3] by simultaneously biasing the two gates of a fully depleted (FD) SOI transistor: if the Si film is thicker than the sum of the depletion regions induced by the two gates, no interaction is produced between the two inversion layers, and the operation of this device is similar to that of two conventional MOSFETs con- nected in parallel. However, if the Si thickness is suffi- ciently reduced, the whole silicon film is depleted and an important degree of interaction takes place between the two potential wells. In such conditions the inversion layer is formed not only at the top and bottom of the silicon slab (i.e., near the two silicon–oxide interfaces), but throughout the entire silicon film thickness. The device is then said to operate in volume inversion, i.e., the carriers are no longer confined to one interface, but are distributed throughout the entire silicon volume. Several authors have claimed that volume inversion * Corresponding author. Tel.: +34-958-246145; fax: +34-958- 243230. E-mail address: fgamiz@ugr.es (F. G amiz). 0038-1101/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2003.12.017 Solid-State Electronics 48 (2004) 937–945 www.elsevier.com/locate/sse