Reducing and Smoothing Power Consumption of ROM-based Controller Implementations Bertrand Le Gal, Aurélien Ribon, Lilian Bossuet, Dominique Dallet IMS Laboratory, UMR CNRS 5218 – University of Bordeaux 351, cours de la Libération, 33405 Talence, France {firstname.lastname}@ims-bordeaux.fr ABSTRACT Interest in automated methodologies increased last decades due to the ever-growing processing complexity and time-to-market constraints. CAD tools prove their efficiency in power consumption management, which is nowadays a major constraint for embedded systems. Efficient low power techniques for Finite State Machine (FSM) design have been proposed for logic-based controllers. In this paper, we explore the circuit power consumption reduction when the FSM is mapped in ROM blocks. The described methodology achieves power reduction of ROM- based controllers through the transformation of don’t care values in the decoder part of the design. This methodology allows a reduction of the number of resource commutations and smoothes them over the processing execution, limiting current spikes. Experiments show that the number of commutation can be decreased from 64% compared to an area-optimized ROM implementation. Categories and Subject Descriptors B.6.1 [Hardware]: Logic Design – Design styles. General Terms Algorithms, Performance, Design. Keywords FSM implementation, ROM-based design, Low power, CAD. 1. INTRODUCTION Time to market pressure coupled to application complexity requires designers to use more and more Computer Aided Design (CAD) tools to speed-up their developments. Automatic algorithmic-to-hardware design generation under constraint may be realized using High-Level Synthesis (HLS) methodologies [1- 2]. These CAD tools are nowadays required to cope the time to market pressure for digital systems [3-4]. To improve designer constraint handling, researches on HLS methodologies proposed solutions to novel design issues like: reliability [5], multi-mode design (single core with multiple functionalities) [6], power consumption [7], etc. Unfortunatly, generated circuits obtained using these methodologies are more complex: the datapath requires more resources (arithmetic, logical, register and multiplexer elements) than hand-optimized ones. As a result, circuit controller complexity explodes  with a high number of resources and states. This complexity increase impacts the architecture performances: a large number of states produces more complex equations, introducing critical path delay issues in circuits. Controller part of circuits may become the limiting factor for the circuit clock frequency and throughput. It has been demonstrated that implementing the controller in a ROM-based design provides constant delay disregarding the number of states and resources to control [8], compared to LUT/logic-based design [9-10]. Moreover ROM-based implementations are efficient on ASIC as well as FPGA technologies, since ROM resources are also available in low cost FPGA [11]. An important part of custom hardware accelerators implemented targeting FPGA or ASIC technologies is integrated in battery powered embedded systems. Power efficiency of circuits is important while designing embedded systems where limited power dissipation and long battery lifetime are crucial requirements. Controllers based on logic or ROM implementations may be responsible for a significant amount of power consumption [12]. Minimizing power consumed by the FSM implementations can significantly reduce the total power. In this paper, we present a power optimization methodology for digital controllers implemented using ROM based designs. Solved problem is different from literatures approaches as we (1) do not consider that the next state computation part of the decoder is the most complex one (2) reduce the consumption spikes over the controller execution. Proposed technique helps in reducing the number of controller output commutations, and smoothing commutations spikes over controller transitions. This article is structured as follows: section 2 presents the literature approaches for controller power optimization, and more precisely on ROM-based implementation of these controllers. Motivations are presented in section 3. Section 4 details the low power approach used to minimize the controller output commutations and to smooth them over the controller transitions. Experimental results validating our technique are reported in Section 5. 2. RELATED WORKS Works reducing power consumption in FSM circuits have been proposed in [9, 12]. These approaches mainly focus on controller state minimization and state encoding problems to reduce the controller area, delay and power consumption. However, most these works were developed considering: 1. Logic-based implementation of controllers 2. Control intensive applications. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. SBCCI’10, September 6–9, 2010, São Paulo, Brazil. Copyright 2010 ACM 978-1-4503-0152-7/10/09...$10.00.