Characterization and modeling of low frequency noise in CMOS inverters E.G. Ioannidis a,b,c , S. Haendler b , C.A. Dimitriadis a , G. Ghibaudo c,⇑ a Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece b STMicroelectronics, rue Jean Monnet, 38921 Crolles, France c IMEP-LAHC, Minatec INPG, Parvis Louis Néel, 38016 Grenoble Cedex 16, France article info Article history: Received 25 October 2012 Received in revised form 30 November 2012 Accepted 4 December 2012 Available online 28 February 2013 The review of this paper was arranged by Prof. A. Zaslavsky Keywords: Low frequency noise CMOS inverter abstract A detailed characterization and modeling of the low frequency noise in a CMOS inverter is presented for the first time. A low frequency noise model for the load current and the output voltage is developed based on the carrier number fluctuations scheme. This model allows obtaining a consistent description of the noise characteristics of CMOS inverters issued from a 45 nm bulk CMOS technology. It should constitute a reliable theoretical framework for further analysis of the impact of time fluctuations on the static and dynamic operation of CMOS inverter based circuits. Ó 2013 Elsevier Ltd. All rights reserved. 1. Introduction The CMOS inverter constitutes the basic element in digital VLSI circuits as a logic NOT gate or in static random access memory (SRAM). With the scaling down of CMOS technologies, the opera- tion of CMOS inverter becomes more subjected to static and dy- namic fluctuations due to device parameter variability as well as to low frequency (LF) and random telegraph noise (RTN), which scale as the inverse of the device area [1–5]. These huge fluctua- tions might jeopardize the CMOS inverter functioning and could reduce the static noise margin in SRAM cell [6]. In MOS devices, it is generally accepted that the LF noise origi- nates either from carrier number fluctuations (CNFs) [7] or from Hooge mobility fluctuations (HMFs) [8]. The CNF noise is due to carrier trapping–detrapping into slow states located in the gate dielectric close to the interface with the channel. The charge fluc- tuations in the gate dielectric could also induce fluctuations of the carrier mobility, giving rise to the so-called correlated mobility fluctuations (CMFs) [9,10]. In small area devices, RTN could even dominate giving rise to strong variability in LF noise in CMOS devices [11–13]. In this work, we address for the first time the detailed character- ization and modeling of the LF noise in a CMOS inverter, considered as a whole device. We first develop in Section 2 a theoretical model for the LF noise in a CMOS inverter within the carrier number fluctuations scheme. Then, in Section 3, we analyze the results of LF noise measurements carried out on CMOS inverters from a 45 nm bulk CMOS technology and discuss them with regard to the proposed LF noise inverter model. Finally, we conclude this work by summarizing our findings and by giving some recommendation for the circuit design application. 2. Theoretical modeling The load current I dd conducted in the CMOS inverter, schemat- ically represented in Fig. 1, can be obtained by equating the conser- vation of the drain currents of the pMOS, I p , and the nMOS, I n , transistors as, I dd ðV in ; V out Þ¼ I n ðV in ; V out Þ¼ I p ðV in ; V out Þ: ð1Þ For each channel, the drain current can be calculated in the gradual channel approximation, using the common source voltage reference, as, I d ðV gs ; V ds Þ¼ Z V ds 0 W L  l eff ðE eff Þ Q i ðV gs ; U c ÞdU c ; ð2Þ where V gs is the gate-to-source voltage, V ds is the drain-to-source voltage, U c is the quasi-Fermi level shift along the channel, W is the channel width, L the channel length, l eff the effective mobility depending on the effective electric field, E eff =(gQ i + Q d )/e si (g  0.5 for electrons and g  0.33 for holes) through the universal mobility law [14,15] (Q d being the depletion charge). The inversion charge Q i can be calculated using the Lambert W function (LW) approximation as [16], 0038-1101/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2012.12.001 ⇑ Corresponding author. E-mail address: ghibaudo@minatec.inpg.fr (G. Ghibaudo). Solid-State Electronics 81 (2013) 151–156 Contents lists available at SciVerse ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse