IJSRSET151680 | Received: 21 December 2015 | Accepted: 26 December 2015 | November-December 2015 [(1)6: 352-357] © 2015 IJSRSET | Volume 1 | Issue 6 | Print ISSN : 2395-1990 | Online ISSN : 2394-4099 Themed Section: Engineering and Technology 352 Hardware & Power efficient Multiplier Geetanjali Sharma, Nitesh Dodkey Department of Electronics and Telecommunication, Surabhi Group of Institution, Madhya Pradesh, India ABSTRACT This paper presents a hardware and power efficient binary multiplier using resource reuse technique. The proposed design uses efficient design of half and full adder circuits which uses less number of logic gates. An array multiplier of n x n needs n rows and n columns of full adder circuits to generate the product term. The proposed design requires only 3 rows of adders to generate the product term. Intermediate product terms are stored in the memory elements (flip flop). As flip flops takes less area and consume less power as compared to adder circuit (combinational circuit), this improves the hardware efficiency and power efficiency of the design. This technique is used to implement a 8 x 8 multiplier and the results are compared with other 8 x 8 array multipliers. Spartan 3 FPGA is used to implement the design. The design is very linear and it can be easily extended to implement large multiplier. Keywords: Power Efficient, Multiplier, Switching Delay, Hardware Efficient and Resource Reuse I. INTRODUCTION Multipliers play an important role in today’s digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier thus making them suitable for various low power and compact VLSI implementation. It is well known that Multipliers consume maximum power in DSP computations [1]. Hence, it is very important for modern DSP systems to design low-power multipliers to reduce the power dissipation. In low- power multiplier design, many researcher experiments & find out results on the reduction of the switching activities [2] have been published. Besides that, a simple and straightforward approach [3] for low-power multiplier is to design a low-power Full Adder to reduce the power dissipation in an array multiplier. The other designs are proposed to reduce the power dissipation in a multiplication operation by interchanging dynamic operands [4] or using partially guarded computation [5]. Furthermore, to minimize power dissipation architectural modification can be used via row bypassing [6] or column bypassing [7] techniques. Based on the concept of theory row and column bypassing techniques for the reduction of the power dissipation, a low-power 2 - dimensional bypassing based multiplier [8] and a low- power row-and- column bypassing-based multiplier [9] are further proposed. However, the introduction of the extra bypassing circuit decreases the ability of minimize the power dissipation, and it also induces extra delay in the circuit. In array multiplier n number of full adder layers are required, where n is the size of the architecture. In this work we have used only three layers of full adders to implement the complete design, this will reduce the area requirement and it will also reduce the power consumption of the design. The paper is organized as follows in section II related work is given, in section III, IV and V array, column bypass and row bypass are discussed respectively. In section VI comparison of different multiplier architecture s are discussed. In section VII conclusion and in section VIII a novel multiplier is briefly explained.