Optimization of Holding Current in 4H-SiC Thyristors Stanislav Soloviev a , Ahmed Elasser, Sarah Katz, Steve Arthur, Zach Stum, and Liangchun Yu General Electric Global Research Center, Niskayuna, NY 12309, USA a soloviev@ge.com, Keywords: thyristor, pulse power device, substrate defects, carrier lifetime, SiC Abstract. Two designs (A and B) of 4H-SiC thyristors for pulse power applications were implemented and characterized in this work. Both designs have the same layout and epi-layer stack except for the anode layers: thyristors with design A (baseline) had a thin (~0.5 µm) anode while devices with design B (optimized) consisted of a heavily doped cap layer (~0.5 µm, ~10 19 / cm 3 ) and ~1.5 µm p-type layer with lower doping (~10 18 /cm 3 ). All devices were fabricated in 4” 4H-SiC substrates (three wafers per each design) and were fully characterized at the wafer level including measurements of forward voltage, blocking voltage, leakage current, and holding current. It was shown that the mean value of the holding current in the thyristors with thin anode was significantly higher (0.7A) than that of the thyristors with thick anode (0.1A), while other parameters had practically the same values. The open circuit voltage decay (OCVD) method was used for measurements of the minority carrier lifetime in order to correlate it with the holding current. Impact of material properties and device design parameters on the holding current is discussed as well. Introduction The SiC thyristor is a promising device for pulse power applications, especially where high voltage, high pulse currents, and high temperature operation are required. The holding current is one of the important thyristor parameters that define the static and dynamic characteristics of the device. The holding current is a function of many parameters including electrical material properties and device geometry. Considering the fact that commercially available SiC material still contains a high density of various types of defects (although significant improvement was achieved in the last decade), it is expected that the defects would affect the electrical material properties and, thus, device performance. There are many publications reporting on the electrical activity of extended material defects such as dislocations, stacking faults, etc. and their impact on the device characteristics. However, most of the studies used simple device structures such as Schottky diodes, p-n diodes, or MOS capacitors to investigate the role of material defects. To the best of our knowledge, no research related to establishing a correlation between material defects and the performance of more complex devices such as transistors or thyristors, was reported so far. In this work we report finding an impact of SiC substrate properties on the holding current of SiC thyristors and present an optimized design of the thyristor that mitigates the impact of non-uniform substrate properties on the holding current. Experiment Two device design structures were implemented. Both designs have the same layout and epi-layer stacks except the anode layer. Design of device A (baseline design) has a single thin (~0.5 µm) uniformly doped anode layer, while the anode design in device B consists of two layers: a heavily doped cap layer (~0.5 µm, ~10 19 / cm 3 ) and a lower doped (~10 18 / cm 3 ) ~1.5 µm thick layer. Cross- sections and epi-layer parameters of the devices are show in Figure 1. Key fabrication process steps are described in Ref [1]. Materials Science Forum Vols. 740-742 (2013) pp 994-997 Online available since 2013/Jan/25 at www.scientific.net © (2013) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/MSF.740-742.994 All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of TTP, www.ttp.net. (ID: 192.35.44.24-18/02/13,20:56:44)