Detailed simulation study of a dual material gate carbon nanotube field-effect transistor Ali A. Orouji à , Zahra Arefinia Electrical Engineering Department, Semnan University, Semnan, Iran article info Article history: Received 19 September 2008 Accepted 15 October 2008 Available online 1 November 2008 PACS: 85.35.p 85.35.Kt 68.65.k Keywords: CNTFET Dual material gate (DMG) Short-channel effects (SCEs) Nonequilibrium Green’s function (NEGF) abstract For the first time, a new type of carbon nanotube field-effect transistor (CNTFET), the dual material gate (DMG)-CNTFET, is proposed and simulated using quantum simulation that is based on self-consistent solution between two-dimensional Poisson equation and Schro ¨ dinger equation with open boundary conditions, within the nonequilibrium Green’s function (NEGF) framework. The proposed structure is similar to that of the conventional coaxial CNTFET with the exception that the gate of the DMG-CNTFET consists of two laterally contacting metals with different work functions. Simulation results show DMG-CNTFET significantly decreases leakage current, drain conductance and subthreshold swing, and increases on–off current ratio and voltage gain as compared to conventional CNTFET. We demonstrate that the potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed short-channel effects like the drain-induced barrier lowering (DIBL) and hot-carrier effect. & 2008 Elsevier B.V. All rights reserved. 1. Introduction Single wall carbon nanotubes (CNTs) have been of great interest for future electronics because of their exceptional electronic and optical properties. They are particularly attractive for high-speed applications due to their quasi-ballistic properties [1,2] and high Fermi velocity (10 6 m/s) [3]. CNTs have been identified as an important subset of one-dimensional (1-D) structures with the highest potential to risk ratio for emerging logic applications such as field-effect transistors (FETs). Consequently CNTFETs attract much attention since their first demonstration [4,5]. CNT transistors scaled down to 10 nm or even shorter have attracted a great deal of interest [6–8]. CNTFETs are ultra-thin body devices [9] that do not suffer from severe mobility degradation as typically observed for silicon MOSFETs with nanometer dimensions [10]. This makes nanotubes extre- mely suitable for aggressive scaling of the channel length well into the nanometer range while preserving long-channel type electrical characteristics [11]. On the other hand, short-channel effects (SCEs) occur when the channel length shrinks due to the increased charge sharing from source and drain. Several novel device structures have been reported in the literature to circumvent the undesirable SCEs in FETs [12]. One of these structures is dual material gate (DMG) FET, that employs ‘‘gate material engineering’’ instead of ‘‘doping engineering’’ to improve both carrier efficiency and SCEs [13–18]. To incorporate the advantages of both DMG and CNTFET structures, we propose a new structure, the DMG-CNTFET, which is similar to that of a conventional coaxial CNTFET [19] with the exception that it is a cylindrical gate consisting of two different metals with different work functions. These two metals merge into cylindrical gate by making them contact laterally. In addition, we select a metal with higher work func- tion as the gate’s material 1, which is close to the source, and a metal with lower work function as material 2, which is close to the drain [13]. Therefore, for the first time in this paper, we have simulated the DMG-CNTFET using 2-D quantum simulation. The simulations have been done by the self-consistent solution of 2-D Poisson– Schro ¨dinger equations, within the nonequilibrium Green’s func- tion (NEGF) formalism. Then we obtain fundamental electrical properties of DMG-CNTFET such as output characteristics, transconductance characteristics, electrostatic potential, electric field, electron velocity, local density of states (LDOS) and elec- tron density. Our results demonstrate that the proposed DMG- CNTFET exhibits significantly reduced SCEs, thus making it a more reliable device configuration compared to the conven- tional CNTFET (C-CNTFET) for high-performance CMOS circuit applications. ARTICLE IN PRESS Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/physe Physica E 1386-9477/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.physe.2008.10.005 à Corresponding author. Tel.: +98 261446 2954; fax: +98 231333 1623. E-mail address: aliaorouji@ieee.org (A.A. Orouji). Physica E 41 (2009) 552–557