Copyright © 1978 American Telephone and Telegraph Company The Bell System Technical Journal Vol. 57, No. 3, March 1978 Printed in U.S.A. Sequentially Companded Modulation for Low- Clock-Rate Speech Codec Applications By S. V. AHAMED (Manuscript received October 7, 1977) The expansion of the step size of a speech codec may be arranged to change as the number of identical consecutive bits starts to increase. This technique causes the codec to respond partially to a fewer number of identical consecutive bits and more dramatically to larger numbers. In contrast to a typical exponential expansion of the step size, the proposed technique, in addition, expands the exponent. For speech, two distinct advantages have been observed: (i) the improvement of higher frequency audio frequency response at the same clock rate and («') the reduction of idle channel noise. In practice we have found that three- and four-bit companding will suffice for a typical 24 kHz, ADM codec. The proposed companding appears to be an acceptable choice between two-, three-, and four- bit companding which leads to better frequency response but worse noise, and four-bit companding which leads to both worse frequency and noise responses. 1. INTRODUCTION The many distinct advantages of companding to encompass the dy- namic range of speech signals are well documented. In most cases, a simple law is used repeatedly to arrive at the companded step size. For instance, in the 37.7 kHz, ADM SLC-40 codec, 1 a nonlinear function of the frequency of occurrence of four identical consecutive bits forces an expansion of the step size. In the two-bit companding described in Ref. 2, the expansion of step size follows a geometric progression. Three bit companding described in Ref. 3, again depends on a base-two geometric series for increasing the step size, when two consecutive bits are the same, and again on the same series with a base-half for decreasing the step size when the bits are of opposite polarity. Most of these systems perform adequately at higher (typically above 32 kHz) clock rates. However, when the clock rate is decreased, the simple fixed rules of companding either offer an unacceptable quantization noise at lower step sizes, or make the 765