Efficient Implementation of Reversible Logic Gates and Full adder in 180 nm MOS Technology Ankit Jain, Ashwin A Kumar, Sameer Aggarwal, Sachin Chhillar, Kirti Gupta Dept. of Electronics and Communication, Bharati Vidyapeeth’s College of Engineering, New Delhi ankit8mar@yahoo.com; ashwinkmr45@gmail.com; windstar.scientist@gmail.com; sachin.chhillar039@gmail.com kirtigupta22@gmail.com Abstract— Reversible logic is highly useful in nanotechnology, low power design and quantum computing. The paper proposes efficient MOS implementation for the basic reversible gates namely, Feynman, Toffoli, and Peres gates and employs the proposed circuits in the reversible full adder design. The proposed implementations have been simulated and compared with their traditional counterparts in terms of transistor count, power consumption, and delay and power delay product. All the simulations are carried out in Tanner EDA using 180 nm CMOS technology parameters. It is found that the proposed implementation of the reversible gates is more efficient than the traditional ones. Keywords: Reversible logic; Transmission gate; Feynman gate; Toffoli gate; Peres gate; Full Adder; Power comparison; Quantum computing. I. INTRODUCTION The advances in VLSI technology have led to an increased demand for high speed, small size devices portable devices. These devices are designed to meet the speed and size requirements which in turn results in high power (heat) dissipation violating the basic low power need of portable devices. Many techniques to satisfy the above mentioned goals have been suggested but their use causes only incremental improvements. In view of this, it is predicted that the Moore’s law [1] is at an end due to the inability of the designers to deal with the power requirements of the future chips. A solution to meet the low-power requirement of the devices is by adopting an entirely new model known as reversible logic. Researchers like Frank [2] believed that the devices based on reversible computing will have far lower power requirements than the traditional irreversible devices. The basic reversible gates namely Feynman [3], Toffoli [4] and Peres [5] have been proposed in literature. This paper presents the MOS based implementation of the basic reversible gates. Also, an efficient implementation for the basic reversible gates is also presented. The paper first provides an overview of the reversible logic along with the traditional MOS based implementations of the basic reversible gates in section II. Thereafter, the MOS circuits of the reversible gates with improved performance are proposed in section III. The reversible full adder is presented in section IV. The performance of the proposed gates and the full adder is compared with the traditional reversible counterparts through simulations using 180 nm CMOS technology parameters in section V. Finally section VI concludes the paper. II. REVERSIBLE GATES The researcher R. Landauer in 1960 demonstrated that high technology circuits and systems constructed using irreversible hardware results in energy dissipation of kTln2 Joules due to one bit loss of information where k is Boltzmann’s constant and T the absolute temperature [6]. In 1973, Bennett, showed that one can avoid KTln2 joules of energy dissipation by constructing circuits using reversible logic gates [7]. Reversible gates have equal number of input and output bits so they do not exhibits one bit loss in contrast to irreversible hardware. These gates generate unique output vector from each input vector, and vice versa, that is, there is a one-to-one mapping between input and output vectors. Based on this principle, different basic reversible gates such as Feynman, Toffoli and Peres have been proposed. Their operation along with the traditional MOS implementation is described below: (i) FEYNMAN gate: It has two inputs (A and B) and two outputs (Y1 and Y2) [3]. It is a 2x2 reversible gate as shown in Fig.1. Its behavior is illustrated in Table I. The output Y1 is equal to the input A while the Y2 is defined as the XOR of the inputs. Fig. 1 Feynman gate