Logic Synthesis for FPGAs of Interpreted Petri Net with Common Operation Memory ⋆ Arkadiusz Bukowiec * Marian Adamski * * University of Zielona G´ora, Institute of Computer Engineering and Electronics, Zielona G´ora, Poland (e-mails: {a.bukowiec, m.adamski}@iie.uz.zgora.pl). Abstract: The method of synthesis of the logic circuit of interpreted Petri net is proposed in this paper. Proposed method is based on the minimal encoding of places. Places are encoded in subsets. Each subset is represented by one color of colored Petri net. Operations assigned to places are placed in memory. It leads to realization of logic circuit in two-level architecture, where the combinational circuit of first level is responsible for firing transitions and the second level memory is responsible for the generation of operations. Such approach allows balanced usage of different kinds of resources available in modern FPGAs. Keywords: Decomposition, FGPAs, Logic circuits, Petri-nets, Synthesis. 1. INTRODUCTION Petri nets (PNs) (Murata (1989); Karatkevich (2007)) are one of the most popular method of Application Specific Concurrent Logic Controllers design (Bili´ nski et al. (1994); Girault and Valk (2003); W¸egrzyn and W¸egrzyn (2011)). Nowadays field programmable gate arrays (FPGAs) are used very often for implementation of logic circuits of such controllers (Milik and Hrynkiewicz (2002); Soto and Pereira (2005)). One of the main features of FPGA is ex- istence of logic elements with restricted number of inputs. From another side, logic functions, describing behavior of such circuit, have much more arguments than number of inputs of typical logic element. One of methods of decreas- ing a number of logic functions depending on big number of arguments is architectural decomposition of logic circuit (Rawski et al. (2005); Barkalov and Titarenko (2010)). Such methods required additional internal variables and very often consume more hardware then single-level imple- mentation of FSM. But, this issue can be resolved by usage of both, logic elements and embedded memory blocks that are available in modern FPGA devices. The method of decreasing of a number of functions de- pending of logic conditions and internal variables of inter- preted Petri net logic circuit is proposed in given article. There is proposed to divide logic functions into two sets. First set contains functions responsible for describing tran- sitions and second one contains functions responsible for operations. The first subset, separately for each subnet, is going to be synthesized as regular logic and implemented using look-up tables (LUTs) and the second one is going to be realized as common memory with use of embedded memory blocks (Bukowiec and Barkalov (2009)). In overall ⋆ This work was supported by the Ministry of Science and Higher Education of Poland. Research grant no. N516 513939 for years 2010- 2013. it leads to balanced usage of different kind of logic re- sources of FPGA device. Also, to minimize the number of functions and variables used to describe these functions the minimal encoding of places is applied. To permit the minimal encoding the Petri net has to be colored (Jensen (1987)). Places colored by the same color create one subset and they are encoded by minimal-length binary code. 2. COLORED INTERPRETED PETRI NET A simple Petri net (Murata (1989); Karatkevich (2007)) is defined as a triple PN =(P,T,F ), (1) where: P is a finite non-empty set of places, T is a finite non-empty set of transitions, F is a set of arcs from places to transitions and from transitions to places: F ⊆ (P × T ) ∪ (T × P ), P ∩ T = ∅. Sets of input and output transitions of a place p ∈ P are defined respectively as follows: •p = {t ∈ T :(t,p) ∈ F }, p• = {t ∈ T :(p,t) ∈ F }. Sets of input and output places of a transition t ∈ T are defined respectively as follows: •t = {p ∈ P :(p,t) ∈ F }, t• = {p ∈ P :(t,p) ∈ F }. A marking of a Petri net is defined as a function: M : P → N.