Synchronous to Asynchronous Conversion of Digital Circuits Ricardo Cassia, Felipe França COPPE/PEE, COPPE/PESC Federal University of Rio de Janeiro Rio de Janeiro, Brazil ricardo@lam.ufrj.br, felipe@ieee.org Vladimir Alves Simple Tech Santa Ana, CA, USA valves@simpletech.com In this work an automated conversion method of synchronous circuits into asynchronous ones is presented. The technique utilizes the synchronous circuit fully synthesized netlist, and employs ASERT - Asynchronous Scheduling by Edge Reversal Timing - for signaling and synchronization between asynchronous functional units, which are extracted from the functional blocks hierarchical organization conceived by the original synchronous circuit designer. The method utilizes CAD tools and standard cells libraries for traditional synchronous circuits in addition to a specific developed software. I. INTRODUCTION Since its debut, asynchronous circuits have been recognized as potential providers of advantages in many different fields over their synchronous counterparts, e.g. lower electromagnetic emission, operation frequency dependent on the average delay instead of the slowest, lower power consumption, easier integration in SoCs [1], more secure cryptographic applications [2]. However, asynchronous circuits design is still an awkward and painful task to perform as the available CAD tools and libraries are targeted for synchronous systems as well as designers are used on doing that way. Lately, different conversion methodologies of synchronous circuits into asynchronous equivalents have been presented in various studies [3, 4, 5] in order to assist the development of this mode. The methodology described in [3] presents a de- synchronization mechanism of a synchronous circuit. In this method, the global clock signal is discarded whereas its tree is removed and a new clock signal is generated locally for each register resultant of a signaling by a four phases handshake, becoming an asynchronous circuit. An automated process which converts synchronous circuits in asynchronous circuits is considered in [4]. In this methodology, much similar to the last described, all the register cells of the circuit are replaced by Doubly Latched Asynchronous Pipeline (DLAP) [6], and a four phase protocol of communication is built between the new mutually dependent elements, so that the data flow is propagated asynchronously. Due to the small granularity of the asynchronous unit, determined by each register, this replacement can impact on a greater amount of area as well as affect the speed of execution given the latency introduced by the four phase communication protocol. The presented work proposes a method of automated conversion of synchronous circuits into equivalent asynchronous circuits, making use of the hierarchical division of the system described by the original designer as a base to identify potential sub-blocks to be transformed into asynchronous units. These asynchronous units are then sub- divided into independent operated branches, increasing the mechanism flexibility and performance. It exploits the human perspective of the original synchronous circuit conceptual functionality as an important starting point for the delimitation of the asynchronous units. The result can be considered as a GALS (Globally Asynchronous, Locally Synchronous) system since registers belonging to one branch are triggered by the same control signal. Section II describes the asynchronous signaling mechanisms that are applied on the presented approach. Section III presents the conversion proposal and the results are analyzed in section IV. II. SIGNALING TOOLS A. Scheduling by Edge Reversal - SER Scheduling by Edge Reversal – SER - is an asynchronous distributed algorithm, originally developed to deal with routing in computer networks [7]. In this work, SER will be used as a signaling and synchronizing mechanism between independent processes (circuits) depending on common shared resources (signals). Section B will present how SER can be applied on the design of asynchronous digital circuits. Consider a neighborhood-constrained system composed of a set of processes and a set of atomic shared resources represented by a connected graph G=(N, E) where N is the set of processes, and E, the set of edges defining the interconnection topology. An edge is present between any two nodes if and only if the two corresponding processes share at least one atomic resource. 1-4244-0157-7/06/$20.00 ©2006 IEEE 365