IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 2, FEBRUARY 2007 135 Design Methodology for Global Resonant -Tree Clock Distribution Networks Jonathan Rosenfeld and Eby G. Friedman, Fellow, IEEE Abstract—Design guidelines for resonant H-tree clock distribu- tion networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described, supporting the design of low power, skew, and jitter resonant H-tree clock distribution networks. Excellent agreement is shown between the proposed model and SpectraS simulations. A case study is pre- sented that demonstrates the design of a two-level resonant H-tree network, distributing a 5-GHz clock signal in a 0.18- m CMOS technology. This example exhibits an 84% decrease in power dissipation as compared to a standard H-tree clock distribution network. The design methodology enables tradeoffs among design variables to be examined, such as the operating frequency, the size of the on-chip inductors and capacitors, the output resistance of the driving buffer, and the interconnect width. A sensitivity analysis of resonant H-tree clock distribution networks is also pro- vided. The effect of the driving buffer output resistance, on-chip inductor and capacitor size, and signal and shielding transmission line width and spacing on the output voltage swing and power consumption is described. Index Terms—H-tree sector, on-chip inductors and capacitors, resonant clock distribution networks, sensitivity. I. INTRODUCTION C LOCK signals in digital systems are simultaneously distributed to physically remote locations across an inte- grated circuit (IC). The clock signal provides a time reference that permits different parts of a circuit to operate in the cor- rect order, thereby producing correct logical operation [1]. A clock signal is usually distributed from a common global source through metal interconnect networks and clock drivers, introducing delay. Unfortunately, the delay at every point on an IC cannot be precisely maintained, resulting in delay uncertainty [2]. Clock skew, which is the difference in the clock arrival times between sequentially adjacent registers, can lead to catastrophic logic failure [1]. Another undesirable effect is clock jitter which occurs when the edges of the clock signal fluctuate in time. This behavior occurs due to imperfections in the clock generator and power supply noise [3]. Previous work treating skew and jitter in resonant clock distribution networks Manuscript received April 27, 2006; revised September 6, 2006. This work was supported in part by the Semiconductor Research Corporation under Con- tract 2003-TJ-1068 and Contract 2004-TJ-1207, by the National Science Foun- dation under Contract CCR-O304574, by the Fulbright Program under Grant 87481764, by a Grant from the New York State Office of Science, Technology, and Academic Research to the Center for Advanced Technology in Electronic Imaging Systems, and by Grants from Intel Corporation, Eastman Kodak Com- pany, Manhattan Routing, and Intrinsix Corporation. The authors are with the Department of Electrical and Computer Engi- neering, University of Rochester, Rochester, NY 14627-0231 USA (e-mail: rosenfel@ece.rochester.edu). Digital Object Identifier 10.1109/TVLSI.2007.893576 Fig. 1. 2002 ITRS predictions for skew and jitter [4]. is provided in [8]–[11]. Changes in the coupling capacitance and variations of the input capacitance of the registers also add random noise and increase jitter. ITRS 2002 predictions regarding skew and jitter for different future technologies are shown in Fig. 1 [4]. According to these trends, by the year 2013 at a critical node technology of 32 nm, the skew and jitter will dominate synchronous performance, consuming 62% of the total clock period. Synchronizing digital circuits at high frequencies has be- come more difficult since interconnect geometries do not scale as easily as transistors, producing longer wire delays. The capacitive load of the clock distribution has significantly increased, requiring a greater number of buffers. Additionally, during each cycle, the entire clock capacitance is charged and discharged to ground, dissipating the stored energy as heat. The focus of this paper is a design methodology for low-power resonant clock distribution networks. To combat these phenomena, clock generation and distribu- tion networks based on LC oscillators in the form of transmis- sion line systems have been considered. In salphasic clock dis- tribution networks [5], a sinusoidal standing wave is established within a transmission line. Coupled standing oscillators of this type are used in [6] to distribute a high frequency clock signal. A similar approach uses traveling waves in coupled transmis- sion line loops [7] driven by distributed cross coupled inverters. Comprehensive and systematic investigation of the impact of width, spacing, and loading of a resonant clock tree on skew and energy consumption is presented in [8] and [9]. In [10] and [11], a resonant global clock distribution network is described, 1063-8210/$25.00 © 2007 IEEE