Optimizing Inductive Interconnect for Low Power Magdy A. El-Moursy and Eby G. Friedman Department of Electrical and Computer Engineering University of Rochester Rochester, New York 14627-0231 Abstract: The width of an interconnect line affects the total power consumed by a circuit. A trade off exists between the dynamic power and the short-circuit power dissipated in inductive interconnect. The optimum line width that minimizes the total transient power dissipation is determined in this paper. A closed form solution for the optimum width with an error less than 5% is presented. For a specific set of line parameters and resistivities, a reduction in power approaching 78% is achieved as compared to the minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined. Keywords: transient power dissipation,inductive interconnect, underdamped systems, short- circuit power, characteristic impedance, dynamic power 1. INTRODUCTION As the feature size of CMOS circuits and wiring has decreased, interconnect design has become an important issue in high speed, high complexity integrated circuits (IC). With the increase in signal frequencies and the corresponding decrease in signal transition times, the interconnect impedance can behave inductively [1], increasing the on-chip noise. Furthermore, considering inductance within the design process increases the computational complexity of IC synthesis and analysis tools. However, inductive behaviour can also be useful. As shown in [3], a properly designed inductive line can reduce the total power dissipated by high-speed clock distribution networks. Clock networks can dissipate a large portion of the total power dissipated within a synchronous IC, ranging from 25% to 75 %[4,5]. The technique proposed here can be used to reduce the overall power being dissipated by long interconnect such as a high- speed clock distribution network or data buss.