26 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 1, JANUARY 2008 Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis Guoqing Chen and Eby G. Friedman, Fellow, IEEE Abstract—Interconnect resistance and inductance shield part of the load capacitance, resulting in a faster voltage transition at the output of the driver. Ignoring this shielding effect may induce sig- nificant error when estimating short-circuit power. In order to cap- ture this shielding effect, an effective capacitance of a distributed load is presented for accurately estimating the short-cir- cuit power. The proposed method has been verified with Cadence Spectre simulations. The average error of the short-circuit power obtained with the effective capacitance is less than 7% for the ex- ample circuits as compared with an model. This effective capacitance can be used in look-up tables or in empirical -factor expressions to estimate short-circuit power. Index Terms—Interconnect, , shielding effect, short-circuit power. I. INTRODUCTION S INCE power has become an important design criterion in integrated circuits, accurate and efficient power estimation is required in the circuit design process. As compared with dy- namic power which is well characterized, short-circuit power is more difficult to model due to the complicated transient be- havior of the short-circuit current [1]. The short-circuit power dissipation in a gate is primarily determined by three factors: input signal transition time, load capacitance, and size of the transistors in the gate. In [2], Veendrick developed a closed-form expression for short-cir- cuit power dissipation in an unloaded CMOS inverter. More accurate device models have recently been adopted to analyze short-circuit power [3], [4]. It is shown in [4] that short-circuit power can be as high as 20% of the total active power in high speed, low voltage circuits. As interconnect coupling becomes more significant in advanced technologies, the impact of crosstalk noise on the short-circuit power is analyzed in [5] by introducing an effective input slew. In these analyses, a lumped capacitor is assumed as the load. With CMOS technology scaling, the interconnect resistance can be comparable to the gate resistance and should be included in the load model. In Manuscript received March 6, 2007; revised June 20, 2007. This work was supported in part by the Semiconductor Research Corporation under Contract 2003-TJ-1068 and Contract 2004-TJ-1207, by the National Science Foundation under Contract CCR-0304574 and Contract CCF-0541206, by the New York State Office of Science, Technology & Academic Research to the Center for Advanced Technology in Electronic Imaging Systems, by the Intel Corporation, by Eastman Kodak Company, by Manhattan Routing, and by Intrinsix Corpo- ration. This paper was recommended by Associate Editor D.Z. Pan. G. Chen is with Intel Corporation, Folsom, CA 95630 USA (e-mail: guoqing. chen@intel.com). E. G. Friedman is with the Department of Electrical and Computer En- gineering, University of Rochester, Rochester, NY 14627 USA (e-mail: friedman@ece.rochester.edu). Digital Object Identifier 10.1109/TCSII.2007.907812 [6], a shaped model is adopted as the load. An effective capacitance of the structure for short-circuit power estimation is described in [7] and [8] to maintain compatibility with popular look-up table or -factor based power models. With increasing on-chip frequencies and longer interconnects, the interconnect inductance can also no longer be ignored. As described in [9], the interconnect inductance also exhibits a shielding effect on the load capacitance, increasing the short-circuit power dissipated by the driver. In [10], an effective capacitance of an load is developed to accurately estimate short-circuit power. This effective capac- itance model is extended in this paper. The importance of the inductive shielding effect is identified and the model is further verified for gates with unaligned multiple inputs. The rest of this paper is organized as follows. In Section II, a distributed network is reduced into a model. From this model, the ef- fective capacitance is determined. In Section III, the proposed effective capacitance model is verified by Cadence Spectre sim- ulations for gates with single and multiple inputs. Finally, some conclusions are offered in Section IV. II. EFFECTIVE CAPACITANCE OF AN INDUCTIVE LOAD Model order reduction techniques are commonly used to an- alyze the timing and power of interconnects to improve simu- lation efficiency. In Section II-A, a model is generated from a distributed tree through a typical model order reduc- tion method—moment matching. In Section II-B, this model is further reduced into an effective capacitance by matching the average charging/discharging current. A. Model Representation of Interconnects In [11], an network is reduced to an model by matching the first three moments ( , , and ) of the admit- tance at the driving point. Similarly, an network can be re- duced to an model by matching the first four moments, as shown in Fig. 1. This reduction, however, can be unrealizable (the value of the circuit element is not positive real). In order to obtain a realizable model, a coefficient is introduced in [12], which is the third order admittance moment without con- sidering the inductance. By matching , , , and , the model parameters can be obtained as [12] (1) (2) (3) (4) 1549-7747/$25.00 © 2007 IEEE