Predictions, Challenges, and Opportunities in CMOS Compatible On-Chip Optical Interconnect Eby G. Friedman Department of Electrical and Computer Engineering University of Rochester, Rochester, New York 14627 Abstract— On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. Predictions of the performance of CMOS compatible optical devices are made based on current state-of-art optical technologies. Based on these predictions, electrical and optical interconnects are compared for delay uncertainty, latency, power, and bandwidth density. I. I NTRODUCTION In deep submicrometer VLSI technologies, it has become increasingly difficult for conventional copper based electrical interconnect to satisfy the design requirements of delay, power, bandwidth, and delay uncertainty. One promising candidate to solve this problem is optical interconnect [1]. A comprehensive comparison between optical and electrical interconnects is described in this paper for different technology nodes. The paper is organized as follows. In section II, a delay-optimal design of RLC interconnect is presented. In section III, pre- dictions of the performance characteristics of next generation optical devices are made based on current technology trends. In section IV, electrical and optical interconnect are evaluated for different design criteria. Some conclusions are offered in section V. II. SCALING OF ELECTRICAL I NTERCONNECT The delay model of an RLC interconnect with repeaters described in [2] is used for the electrical interconnect anal- ysis [3]. Three degrees of freedom (the wire width, and the number and size of the repeaters) are explored in the electrical interconnect design process to achieve the minimum delay. The minimum delay per unit length is approximately in the range of 20 to 22 ps/mm for all of the technology nodes of interest. III. ON-CHIP OPTICAL DATA PATH Introducing optical interconnects into VLSI circuits requires compatibility with CMOS technology. Due to the absence of an efficient silicon-based laser, only those configurations that utilize an external laser as a light source are considered. A diagram of an optical interconnect system is shown in Fig. 1. Considering compatibility with a CMOS technology, a practical solution is a 1.5 μm wavelength light source with a silicon modulator and a SiGe or Ge photo-detector. Unlike electrical devices, optical devices are not readily scalable due to the light wavelength constraint. The performance and integration ability of optical devices, however, are expected to be further improved by technology inventions and structural optimization. A transmitter is composed of an electro-optical modulator and a driver circuit. The design of a fast and cost efficient CMOS compatible electro-optical modulator is one of the most challenging tasks on the path towards realizing on-chip optical interconnects. This research was supported by the National Science Foundation under Contract No. CCR-0304574. Laser Optical modulator Waveguide Photo detector Electrical logic cell Driver Electrical logic cell Amplifier On-chip Transmitter Receiver Fig. 1. An on-chip optical interconnect data path. For a specific operating wavelength of 1.5 μm, low refrac- tive index strip polymer waveguides are assumed with a core cross section of 1.5 μm×1.5 μm. The core index and cladding index are 1.6 and 1.1, respectively. The mode effective index is 1.48. The receiver has two components: a photo-detector and an amplifier. Interdigitated SiGe p-i-n or metal semiconductor metal (MSM) detectors are considered due to the fast response and reasonable quantum efficiency of these structures. The performance of future detectors is projected based on a model proposed by Averine et al. [4]. The detector response time is expected in the near future to drop significantly, from tens of picoseconds to a few picoseconds. IV. ELECTRICAL VS. OPTICAL INTERCONNECTS Different criteria used in the design of the two intercon- nect systems described in sections II and III are compared, including delay uncertainty, latency, power dissipation, and bandwidth density. The interconnect length is 10 mm. Delay uncertainty is caused by geometric process variations and environmental changes. Variations in the environment include power/ground noise, temperature fluctuations, and crosstalk coupling. All of the variations are assumed to be random with a normal distribution. The delay and 3σ value for different parts of a 1 cm optical data path are listed in Table I. A comparison of the standard deviation of the delay of the electrical and optical interconnect is shown in Fig. 2. The delay uncertainty of the optical interconnect is expected to be lower in future technology nodes. The delay uncertainty of the electrical interconnect, in contrast, is expected to slowly increase in future technology nodes due to the greater number of repeaters. For data to be correctly latched at the receiving register, certain setup and hold constraints should be satisfied. The delay uncertainty is assumed to not exceed 80% of the clock period. Since no register-like device can be inserted into an optical data path, the delay uncertainty provides an upper bound on the optical channel bandwidth. As listed in Table II, the delay of the electrical interconnect remains approximately fixed for all technology nodes. The delay of the optical