ENOC 2011, 24-29 July 2011, Rome, Italy Experimental results on the quantization in the ADC device for a ZAD-strategy controlled DC-DC Buck converter Fabiola Angulo * , Fredy E. Hoyos * and Gerard Olivar ** * Department of Electrical and Electronics Engineering & Computer Sciences ** Engineering Mathematics Research Laboratory Universidad Nacional de Colombia, Manizales, Colombia Summary . The bit quantization mechanism that occurs in an Analog-to-Digital Converter (ADC), which is a previous step in a digitally controlled DC-DC buck converter is analyzed with detail. Many studies have been devoted to analyzing the Zero Average Dynamics (ZAD)-controlled strategy for converters, but they did not include this important hardware consideration in the modeling. Numerical simulations yielded to some disagreements between numerics and experiments. This is basically due to the high sensitivity to duty cycle values which are computed with the ZAD strategy. This was partially solved with an additional control step so-called Fixed Point Induced Control (FPIC) which was presented at the previous ENOC meeting in Saint Petersburg. Now, in our communication we explicitly introduce the ADC model and we obtain good agreement between experimental and numerically-computed bifurcation diagrams without the help of FPIC control. Introduction In the last decade, ZAD strategy has been developed for controlling DC-DC converters. This controller uses a sliding surface defined as a linear combination of the error and its derivative, which is forced to have a zero average. Previous theoretical and numerical studies have shown that ZAD strategy offers two important advantages (like sliding-mode control): very low error and fixed switching frequency [1]. However, sometimes, numerical and analytical results do not agree with those from experimental set-ups. Implementations based on DSP and FPGA technologies have shown different qualitative and quantitative behavior. Our main hypothesis regarding the discrepancy between real and simulated results is that it is basically due to the quantization process, which is neglected in the modeling stage. Quantization is the process by which a continuous range of values is approximated by a set of discrete symbols or values. Some authors have included digitalization effects of analog-to-digital (A/D) and digital-to-analog (D/A) converters in different systems, linear or nonlinear (such as power converters). In this communication, we introduce a DC-DC buck converter controlled by the ZAD strategy, explicitly including the ADC process. Resolution is the main parameter analyzed. The final version of the full paper will be organized as follows: the introduction will include the mathematical framework for analysis and control. Section 2 will briefly explain the main characteristics of the ADC process. Section 3 will show a detailed analysis of the ZAD-controlled buck converter, including different (bit) resolution bifurcation diagrams, transient dynamics and coexistence of attractors. Finally, conclusions will be stated in the last section. DC-DC Buck converter with ZAD strategy A simplified diagram of the closed-loop buck converter is shown in Figure 1(a). Its main feature is that the output value V o is lower than the source V in (step down converter). Switches S 1 and S 2 operate in a complementary way, i.e. when S 1 is open, S 2 is closed, and viceversa. The mathematical model can be expressed in compact form as:  ˙ x 1 ˙ x 2  =  -1 RC 1 C -1 L 0  x 1 x 2  +  0 Vin L  u (1) where x 1 = V C , x 2 = I L and u belongs to {0, 1}. The next step is to design a control strategy so that the load voltage V 0 is regulated to a desired value. To solve this regulation problem, it is necessary to compute the time (d) when the switch S 1 is ON (u =1) in each previously defined sampling time T (d ∈ [0 T ]). Time d is known as the duty cycle and we will normalize it as D = d/T (D ∈ [0 1]). The control strategy we use is based on the concept of Zero Average Dynamics on the output (ZAD) [2]. The ZAD-strategy can be summarized as follows. First, choose a sampling time T and a surface s(x)=0 in the state space; second, force s(x(t)) to have zero average in each sampling time; and finally, compute the duty cycle. As reported (a) Scheme of a ZAD-controlled Buck converter. (b) Scheme of the Analog-to-Digital conversion process. Figure 1: ZAD-controlled Buck converter with ADC.