IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 _______________________________________________________________________________________ Volume: 03 Issue: 11 | Nov-2014, Available @ http://www.ijret.org 514 IMPLEMENTATION OF LATCH TYPE SENSE AMPLIFIER A. Hemaprabha 1 , K. Vivek 2 , M. Vaijayanthi 3 , S. Sabeetha 4 1 Student, ECE, Manakula Vinayagar Institute of Technology, Puducherry, India 2 Asst. Professor, ECE, Institute Manakula Vinayagar Institute of Technology, Puducherry, India 3 Student, ECE, Manakula Vinayagar Institute of Technology, Puducherry, India 4 Student, ECE, Manakula Vinayagar Institute of Technology, Puducherry, India Abstract Sense amplifiers plays an important role in memories like Dynamic Random Access (DRAM) and Static Random Access (SRAM) for read and write operations. A sense amplifier compares the bit line voltage and its complement amplifies it to rail to rail output voltages. In this project, we mainly concentrated on the write operation. Sense amplifier is one of the peripheral circuits in memories that are placed in each column of the memory array. In this project, we discuss some of the sense amplifiers circuits and they are simulated in SPICE. An analytical model has been derived and simulated using 90nm CMOS technology with a supply voltage of 1.2v. When the input voltage difference of a sense amplifier is greater than the offset voltage (V OS ), the sense amplifier correctly detect the signal and amplifier it to correct logic levels. In an ideal case, the offset voltage of a sense amplifier is zero. Therefore, the sense amplifier can correctly sense the voltage present in the input bitlines, unless the differential bitline voltage is zero. Practically, the offset voltage is not zero because of the mismatch between the transistors. Hence, the differential bitline voltage must be greater than the offset voltage of the sense amplifier for correct sensing operation. Sensing delay, latching delay is one of the important factors in sense amplifier design. So the sense delay and latching delay of sense amplifier has been calculated for various supply voltages. Finally, the current mode sense amplifier has low sensing delay and latching delay compared to other latch type sense amplifiers. Keywords: Sense amplifier, DRAM, SRAM, SPICE, CMOS --------------------------------------------------------------------***---------------------------------------------------------------------- 1. INTRODUCTION Sense amplifier plays an important role in the read operation of data stored on memory cells. It has two input bitlines (bl and blb). One of the bitline is used to read the data from particular memory cell while the other input bitline is used as a reference line. It senses the voltage from a bit line which represents a data bit (1 or 0) stored in a memory cell and amplify the small voltage swing to recognizable logic levels There is one sense amplifier for each column of memory cells. It is the only analog circuits on a digital memory chip. If the sense amplifier is not designed properly it may leads to undesired data output while reading the data in the memory. This work presents a several sense amplifiers using 90nm CMOS technology. 2. CONVENTIONAL SENSE AMPLIFIERS 2.1. NMOS Sense Amplifier Sense amplifier is connected to a pair of bitlines. One is the output data from a particular cell, while the other is used as a reference line. When the voltage on a wordline (Wl) goes high, the transistor is attached to the wordline, connecting respective capacitor to the associated bitline. Then the capacitor discharges or shares its stored charge with the bitline. This charge sharing causes the voltage of the bitline either to increase or decrease. The sense amplifier senses this change and pulls the bitline voltage either to „1‟ or „0‟. The sense amplifier which is made by using n-channel MOSFET is called as n-MOS sense amplifier. The technology used here is 90nm. The width of the n-channel MOSFET is 1um and the width of the p-channel MOSFET is 2um. The ratio of W/L is 10/1. The schematic diagram of n-MOS sense amplifier is shown in Fig.1 The charge or absence of charge on the capacitor (Cmbit) changes the voltage on the bitlines. Consider we are accessing (reading) the data in one of the cell in array 0. So, the sense amplifier sense the bitline from array 0 (bitline 0) and the bitline from array 1 (bitline 1) is used as a reference. The bitlines are precharged to half of the supply voltage (Vdd/2) before start sensing. The bitlines have large number of capacitive loads. Because of large loads, the bitlines swing slowly. To reduce this delay, the bitlines are precharged to Vdd/2. Here equilibrate signal (Eq) is used to setting both the bitlines to Vdd/2. The data in the cell can be accessed by setting word line (Wl) line high, which turns on the Mn7. The storage capacitor (Cmbit) contains zero, so we reading out zero. So, the bitline 0 discharges from the precharged value. Evaluation of the bitline begins when sense_N is driven high, causing NLAT to go low. If the bitline0 fell from precharged value, the n- sense amplifier would pull the bitline 0 to low. The simulation result for reading out „0‟ using NMOS sense amplifier is shown in Fig.2