922 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 4, APRIL 2014 Single-Bit Pseudoparallel Processing Low-Oversampling Delta–Sigma Modulator Suitable for SDR Wireless Transmitters Safar Hatami, Member, IEEE, Mohamed Helaoui, Member, IEEE, Fadhel M. Ghannouchi, Fellow, IEEE , and Massoud Pedram, Fellow, IEEE Abstract— The oversampling requirement in a delta–sigma modulator (DSM) is considered one of the limiting factors toward its employment in current high-frequency applications, such as wireless software defined radio (SDR) systems. This paper advances that the critical requirement for DSMs is high-frequency processing and not a high-oversampling ratio. A single-bit semiparallel processing structure to accomplish the high-frequency processing is proposed in this paper. Using the suggested low-oversampling digital DSM architecture, high- speed, high-complexity computations, which are normally required for wireless applications, are executed simultaneously. This facilitates the design of embedded SDR multistandard transmitters using commercially available digital processors. The most favorable application of the proposed single-bit DSM is to build an radio frequency transmitter that includes a one-bit quantifier with two-level switching power amplifier for both high linearity and high efficiency. Performance analysis is carried out by using MATLAB simulations, which shows a reduction of the oversampling ratio by a factor of 16 (for a baseline oversampling ratio of 256) with the same signal-to-noise ratio (SNR). The proposed DSM is also implemented on a field-programmable gate array (FPGA) board and its performance is validated by using a code division multiple access signal. The bandwidth of the output signal is increased four times without increasing the processing frequency. Simultaneously, quality of the output signal remains the same but FPGA resource usage is increased by a factor of three. Index Terms— Delta–sigma modulation, field-programmable gate array (FPGA), oversampling, parallel processing. I. I NTRODUCTION O VERSAMPLING has become a popular technique for data conversion [1], [2]. The outstanding linearity of delta–sigma modulators (DSMs) is the main reason for the popularity of these modulators in modern electronic compo- nents such as data converters [3], frequency synthesizers [4], Manuscript received April 2, 2012; revised July 31, 2012 and January 11, 2013; accepted February 24, 2013. Date of publication May 24, 2013; date of current version March 18, 2014. This work was supported by the Informatics Circle of Research Excellence, the Natural Sciences and Engineering Research Council of Canada, and the Canada Research Chairs Program. S. Hatami and M. Pedram are with the Department of EE-Systems, University of Southern California, Los Angeles, CA 90089 USA (e-mail: shatami@usc.edu; Pedram@usc.edu). M. Helaoui and F. M. Ghannouchi are with the Intelligent RF Radio Laboratory, Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB T2N 1N4, Canada (e-mail: mhelaoui@ucalgary.ca; fghannouchi@ieee.org). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2013.2256808 and switched-mode power supplies. However, achieving this degree of linearity comes at the cost of a large oversampling ratio and, therefore, need for high-speed processing. The over- sampling requirement in a DSM discourages its employment in current compute-intensive applications, such as software defined radio systems. Emerging applications have encouraged designers to develop highly linear converters with large input bandwidths [5]–[8]. One approach is through the use of higher order modulators and lower oversampling ratios. The disadvantage of this approach is the instability of high-order DSMs [15]. Several researches have utilized the concept of multirate sig- nal processing to reduce the oversampling ratio. A Hadamard transform is used [10], [11] to decompose the input spectrum into several sub-bands, which are then applied to separate DSMs, whose outputs are subsequently recombined. This paper uses two DSMs/output bit, which is inefficient in terms of the die area when implemented using radio frequency (RF) integrated circuits technology. An area-efficient architecture [12] is developed by com- bining multiple DSMs in parallel, along with analog pre- processing of the input signal and digital postprocessing of the output signals. Through interconnected modulators working in parallel with each running at the same clock, a new parallel processing DSM (PDSM) was proposed in [13]. A time inter- leaved sigma–delta architecture was used in [14] to increase bandwidth of the converter with a lower hardware complexity. In this paper, an alternative approach, also based on parallel processing, is described. However, multiple DSMs are not used. The proposed PDSM implements combined and sim- plified processing steps for n sequential clocks of a regular DSM (n closed-loop computations). A PDSM that combines n closed loops generates n bits/clock cycle. The highest sam- pling frequency of the proposed PDSM is now shifted to one multiplexer, which is the same as the sampling frequency of the traditional single-bit DSM. The other processing element of PDSM works n times slower compared with traditional single-bit DSM. The favorable application of the proposed PDSM is an RF transmitter that integrates a one-bit quantifier and a two- level switching power amplifier (PA) to attain high linear- ity. Through the proposed low-oversampling DSM, envelope signals in wireless applications, e.g., orthogonal frequency- 1063-8210 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.