Full 3D Statistical Simulation of Line Edge Roughness in sub-100nm MOSFETs A. Asenov * , A. R. Brown and S. Kaya † Device Modelling Group, Dept. of E&EE, University of Glasgow, G12 8LT, Scotland, UK † SEECS, Russ College of Engineering, Ohio University, Athens, OH 45701, USA * e-mail: A.Asenov@elec.gla.ac.uk, Tel: +44 141 330 5217, Fax: +44 141 330 5236 Line Edge Roughness (LER), caused by tolerances inherent to materials and tools used in lithography processes, is not a new phenomenon. Yet, the imperfections caused by LER have caused little worry over the years since the critical dimensions of MOSFETs were almost two orders of magnitude larger than the roughness. However, as the aggressive scaling of Si-MOSFETs continues to the sub-100 nm regime, LER does not diminish but constitutes an increasingly larger fraction of the gate length. Indeed, at the end of the SIA Roadmap [1], MOSFETs with gate length as small as 20 nm are anticipated, making LER one of the critical problems for ULSI, where millions of devices must operate in very strict margins on a single chip. Due to the lesser importance of LER previously, efforts to model and incorporate this effect into device simulations were either totally absent or limited in terms of realism and sophistication [2-4]. The massive computational resources needed to statistically study this problem was another impediment. Even the most recent works treat the problem in a simplified fashion in a ‘square wave’ approximation for the gate edge [2,3]. The simple statistical approach adopted by Oldiges et al. [4] is also based on 2D simulations, hence suffering from similar limitations. However, LER is a 3D, stochastic effect, which requires a more sophisticated approach to modelling. Here, we present a full-3D simulation approach to investigate the impact of gate LER in MOSFETs in a statistical manner. We study LER induced intrinsic variations in the off- and on-state characteristics of sub-100 nm MOSFETs. In our simulations LER is specified in terms of two statistical parameters: its RMS amplitude (∆) and correlation length (Λ). Data collected from various processes (Fig.1) show that it will be difficult to reduce LER (~3∆) below the 5 to 6 nm limit, i.e. ∆≈2 nm. This value is larger than the Roadmap requirement for devices below 100 nm. In contrast with ∆ values regularly reported in literature, significantly less is known regarding Λ, which is reported to vary between 10 and 50 nm [4]. Our recent analysis on actual LER data obtained from e-beam [5] and EUV [6] lithography processes (Fig. 2) indicate that Λ is of the order of 20 to 30 nm. With such reliable statistical data at hand, we reconstruct realistic source/drain junctions in 3D MOSFET simulations using a 1D Fourier synthesis approach (Figs. 3&4). Thus we incorporate the 3D and statistical nature of LER in a single simulation framework, efficient enough to obtain statistics from a sample of 200 device per data point. Devices considered in this work are properly scaled for sub-100 nm operation and assume a Gaussian autocorrelation function for LER. We demonstrate (Figs.5-9) that LER can lead to considerable intrinsic fluctuations in on- and off-current and threshold voltage [10]. In particular, the off-current characteristics are extremely sensitive to LER in 30 nm MOSFETs. Fluctuations become larger as LER parameters increase or when devices are scaled down. When the devices are scaled to 30 nm channel length, the standard deviation of threshold voltage becomes similar in magnitude to those resulting from random dopants [11] and may hamper the integration of this generation of devices, especially when considered in conjunction with the random dopant effects (Fig.12). References [1] Semiconductor Industry Association, SIA Roadmap—Lithography, 147, (1999) [2] T. Linton, M.Giles and P. Packan, Silicon Nanoelectronics Workshop, 82, (1998) [3] T. Linton, S. Yu and R. Shaheed, VLSI Design, in press. [4] P. Oldiges et al., Proc. SISPAD, Seattle, USA, 131, (2000) [5] S. Thoms, D. Macintyre and M. McCarthy, Microelec. Eng., 41/42, 207, (1998) [6] G. Cardinale et al., J. Vac. Sci. Tech. B, 17, 2970, (1999) [7] S. Mori et al., J. Vac. Sci. Technol. B, 16, 3739. (1998) [8] S. Winkelmeier et al., Proc. SPIE, in press. [9] M. Yoshizawa and S. Moriya, Electr. Lett., 36, 90, (2000) [10] A. R. Brown,. S. Kaya, A. Asenov and T. Linton, Silicon Nanoelectronics Workshop, Kyoto, Japan, (2001) [11] A. Asenov, IEEE Trans. Elec. Dev., 45, 2505, (1998)