492 IEEE TRANSACTIONS ONNANOTECHNOLOGY, VOL. 8, NO. 4, JULY 2009 Fabrication and Characteristics of Self-Aligned Dual-Gate Single-Electron Transistors Dong Seup Lee, Student Member, IEEE, Sangwoo Kang, Member, IEEE, Kwon-Chil Kang, Student Member, IEEE, Joung-Eob Lee, Student Member, IEEE, Jung Hoon Lee, Student Member, IEEE, Kwan-Jae Song, Dong Myong Kim, Member, IEEE, Jong Duk Lee, Member, IEEE, and Byung-Gook Park, Member, IEEE Abstract—Single-electron transistors that have electrical tun- neling barriers are fabricated, and Coulomb oscillation peaks and negative differential transconductance are observed at room tem- perature (300 K). Operation characteristics and multioscillation peaks are further investigated at low temperature (80 K). The pe- riod of Coulomb oscillation is 2.3 V due to an ultrasmall control gate capacitance, and oscillation peaks are shifted through the side gate bias, which is explained by the derived stability plot for dual-gate structures. Even with the side gates electrically floating, the device still operates as a single-electron transistor since the p-n junction barrier plays a role of tunneling barrier. In addition, by changing the bias condition, double dots are formed along the channel and peak splitting is observed. Index Terms—Coulomb diamond, Coulomb oscillation, double dot, single-electron transistor (SET). I. INTRODUCTION S INGLE-ELECTRON TRANSISTORS (SETs) are consid- ered as one of the promising devices for future ultralow power and high-density systems [1], [2]. Especially, silicon- based SETs have advantages in the fabrication and design of CMOS/SET hybrid circuits. Due to its potential, it has been ac- tively investigated by many researchers, and various structures have been introduced [3]–[5]. However, low operation tempera- ture and poor fabrication controllability still remain as obstacles to practical application. In this respect, compared with other structures, dual-gate SETs are advantageous because the height of the tunneling barriers can be controlled through the external bias, and the quantum dot size is further decreased by the elec- tric field effect [6]–[8]. In addition, the device can be fabricated with CMOS compatible and self-aligned process. In this paper, self-aligned dual-gate SETs are fabricated with optimized parameters for room-temperature operation. At 80 K, Manuscript received June 13, 2008; revised September 17, 2008. First published February 27, 2009; current version published July 9, 2009. The review of this paper was arranged by Associate Editor D. Litvinov. This work was sup- ported by the BK21 Program by the Ministry of Commerce, Industry and Energy under the “Functional Nano-Device & Circuit Application Technology Devel- opment Project.” D. S. Lee, K.-C. Kang, J.-E. Lee, J. H. Lee, J. D. Lee, and B.-G. Park are with the Inter-University Semiconductor Research Center, School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea (e-mail: candle0101@naver.com; boyz27@snu.ac.kr; lspace00@gmail.com; justin82@snu.ac.kr; jdlee@snu.ac.kr; bgpark@snu.ac.kr). S. Kang is with the Hynix Semiconductor, Ichoen-si 467-701, Korea (e-mail: swk1230@gmail.com). K.-J. Song and D. M. Kim are with the School of Electrical Engineer- ing, Kookmin University, Seoul 146-702, Korea (e-mail: goodday_2003@ naver.com; dmkim@kookmin.ac.kr). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TNANO.2009.2016209 Fig. 1. (a) Structure and (b) top view of the fabricated device. The structure of the device is similar to conventional CMOS. output characteristics of the fabricated devices are investigated in the various bias conditions. Double-dot-mode operation is also demonstrated by changing the role of control gate and side gate. II. DEVICE STRUCTURE AND F ABRICATION PROCESS The basic device structure and main fabrication process flow are similar to the device presented in [8] by our group, but the process parameters are modified to decrease the size of the quan- tum dot and improve its functionality, as shown in Fig. 1. The devices are fabricated on a p-type, separation-by-implantation- of-oxygen (SIMOX) (1 0 0) wafer. The thickness of the buried oxide and initial top silicon layer is 360 and 200 nm, respec- tively. The top silicon layer that has a boron concentration of 1 × 10 15 cm −3 is thinned down to 20 nm through repeated thermal oxidation and removal of the grown oxide. To prevent dopants acting as random barriers or quantum dots, no additional channel doping is conducted. The active region of which mini- mum width is 17 nm is defined through e-beam/photo mix-and- match lithography and subsequent plasma silicon etch, as shown in Fig. 2. Next, 2.5 nm thermal oxide is grown at 850 ◦ C for further narrowing the active width and curing plasma etch dam- age. Afterwards, 22 nm control gate oxide and 105-nm amor- phous silicon are deposited by plasma-enhanced chemical vapor deposition (PECVD) and low-pressure chemical vapor deposi- tion (LPCVD), respectively. To form the control gate, e-beam/ photo mix-and-match process is carried out, and 20 nm mini- mum gate length is obtained. To isolate the control gate from the side gates, 10 nm intergate oxide is formed through thermal oxidation of the control gate, which reduces the control gate 1536-125X/$25.00 © 2009 IEEE Authorized licensed use limited to: Kookmin University. Downloaded on July 21, 2009 at 22:24 from IEEE Xplore. Restrictions apply.