P. Sirisuk et al. (Eds.): ARC 2010, LNCS 5992, pp. 219–230, 2010. © Springer-Verlag Berlin Heidelberg 2010 Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing * Esam El-Araby, Vikram K. Narayana, and Tarek El-Ghazawi NSF Center for High-Performance Reconfigurable Computing (CHREC), The George Washington University, Washington, DC 20052, USA esam@gwmail.gwu.edu, {vikram,tarek}@gwu.edu Abstract. High-Performance Reconfigurable Computers (HPRCs) are parallel machines consisting of FPGAs and microprocessors, with the FPGAs used as co-processors. The execution of parallel applications on such systems has mainly followed the Single-Program Multiple-Data (SPMD) model; however, overall system resources are often underutilized because of the asymmetric dis- tribution of the reconfigurable (co-)processors relative to the (main) processors. Furthermore, with the introduction of HPRCs containing multi/many-core tech- nologies, underutilization of system resources becomes more obvious especially for multi-tasking and multi-user usage. To address the asymmetry problem, we propose a resource virtualization solution based on Partial Run-Time Recon- figuration (PRTR). The proposed technique allows space, time, and/or space- time sharing of the reconfigurable (co-)processors among the (main) processors and thus increasing the overall system utilization. We show the effectiveness of the proposed concepts through a stochastic execution model verified with ex- perimental implementations on the Cray XD1 platform. The results demonstrate favorable performance as well as scalability characteristics. Keywords: Dynamic Partial Reconfiguration, Hardware Virtualization, High Performance Computing, Reconfigurable Computing. 1 Introduction Recent years have witnessed the introduction of stand-alone general purpose Recon- figurable Computers (RCs) as well as parallel reconfigurable supercomputers called High-Performance Reconfigurable Computers (HPRCs). Examples of such super- computers are the SRC-7 and SRC-6 [1], the SGI Altix/RASC [2] and the Cray XT5 h and Cray XD1 [3]. These systems are capable of delivering high performance as well as maintaining flexibility, due to the use of FPGAs. The FPGAs are mainly used as co-processing element(s) (CPE) to the main processing element(s) (MPE) in order to accelerate critical functions in hardware. Several efforts have proved the significant performance speedups obtained by these systems for many different appli- cations [4]. Applications for HPRCs are mainly developed using the Single-Program * This work was supported in part by the I/UCRC Program of the National Science Foundation under Grant No. IIP-0706352.