Torc: Tools for Open Reconfigurable Computing Neil Steiner, 1 Aaron Wood, 1 Hamid Shojaei, 2 Jacob Couch, 3 Peter Athanas, 3 and Matthew French 1 1 Information Sciences Institute University of Southern California Arlington, Virginia neil.steiner@isi.edu, awood@isi.edu, mfrench@isi.edu 2 Department of Electrical and Computer Engineering University of Wisconsin-Madison Madison, Wisconsin hshojaei@wisc.edu 3 Department of Electrical and Computer Engineering Virginia Tech Blacksburg, Virginia jacouch@vt.edu, athanas@vt.edu Abstract—Configurable computing researchers are often sidetracked by tool and infrastructure needs while pursuing unique and novel work, and frequently resort to simplified device models for lack of real architectural data. To address these issues, we present and describe Torc, an open-source C++ infrastructure and tool set for reconfigurable computing, suitable for custom research applications, for CAD tool devel- opment, and for architecture exploration. The Torc infrastructure can read, write, and manipulate EDIF, BLIF, and XDL netlists, as well as Xilinx bitstream packets (without however understanding configuration frame internals). The Torc tools include placing and routing for full or partial designs, along with additional capabilities to facilitate design manipulation and analysis. In support of these capabilities, Torc provides exhaustive wiring and logic information for all major Xilinx devices, derived from non- proprietary sources. We believe that Altera architectures and designs could be similarly supported if the necessary data were available, and we have successfully used Torc internally with custom architectures. We present some examples of capabilities built with Torc, including an EDIF obfuscator, an XDL sub-circuit extractor, and a third-party partial reconfiguration tool. Torc is open- source software and is available at http://torc.isi.edu. I. I NTRODUCTION Modern FPGAs are complex devices, and the designs targeting them are often described in complex file formats. As a result, researchers frequently have to work with simpler files and models, or have to invest significant development effort into parsers, object models, and large routing graphs. Unfortunately, real devices are much messier to work with than simple models suggest, and the relevance of tools built upon such models is proportionately reduced. Work involving large System-on-Chip designs led us to search for tools that could manipulate netlists in com- prehensive ways. Specifically of interest was support for commercial netlist formats such as EDIF, XDL, and VQM. The conclusion was that such capabilities were generally unavailable, except to device manufacturers and large EDA companies, and we therefore began to develop our own tools. We expound here on work first announced in [1]. One aim is to provide real device data, increasing the relevance of CAD tools that researchers develop. Another aim is to provide a framework for device and design data, allowing researchers to focus on the unique and novel as- pects of their work, without being waylaid by infrastructure development. Promising uses for Torc include CAD tool research, device architecture exploration, hardware autonomy re- search, partial runtime reconfiguration, as well as tools for low-power CAD, radiation mitigation, security / anti-tamper, health monitoring, et cetera. We divide the Torc code base into two parts: Application Programming Interfaces (APIs) that provide access to both device and design data, and CAD tools that process and manipulate design and implementation data. The APIs form the foundational core of Torc: They provide importers, exporters, and object models for EDIF and BLIF netlists, for XDL netlists, and for bitstreams. They also provide device models and data for all Xilinx devices since the Virtex family. Because device manufacturer data is often sensitive and proprietary, we ensure that the data and capabilities underlying Torc are derived from non- proprietary sources. The Torc tools build upon the foundation provided by the APIs: They presently include routing, placing, unpacking, and combinational path extraction, with packing capabilities to follow in the near future. We provide background information in Section II. We then describe the Torc design in Section III, the API in Section IV, and the associated CAD tools in Section V. Applications follow in Section VI, and we conclude in Section VII. II. BACKGROUND For the sake of clarity, we first describe file formats relevant to Torc, and then delve into prior and related work, and an overview of device architecture and terminology. A. File Formats BLIF (Berkeley Logic Interchange Format): Prevalent academic format for synthesized netlists and optimizations.