A Simulator of Small-Delay Faults Caused by Resistive-Open Defects Alejandro Czutro * Nicolas Houarche ** Piet Engelke * Ilia Polian * Mariane Comte ** Michel Renovell ** Bernd Becker * * Albert-Ludwigs-University Georges-K¨ ohler-Allee 51 79110 Freiburg im Breisgau, Germany ** LIRMM – UMII 161 Rue Ada 34392 Montpellier, France Abstract We present a simulator which determines the coverage of small-delay faults, i.e., delay faults with a size below one clock cycle, caused by resistive-open defects. These defects are likely to escape detection by stuck-at or transition fault patterns. For the first time, we couple the calculation of the critical size of a small-delay fault with the computation of the resistance range of the corresponding resistive-open de- fect for which this size is exceeded. By doing so, we are able to extend probabilistic fault coverage metrics initially developed for static resistive bridging faults to small-delay defects. Keywords: Small-delay defects, resistive opens, proba- bilistic fault coverage, bridging fault simulation. 1 Introduction Small-delay faults are not adequately covered by stuck-at and transition test sets [1]. Low-resistance interconnect open defects are a major source of small-delay faults [2, 3]. Hence, an accurate assessment of a test set’s coverage of small-delay faults should take into account the physical pa- rameters of the open defects causing the potential defects. State-of-the-art small-delay fault simulation approaches de- termine for every considered fault site the sizes of the fault for which the fault is covered by a test set [4, 5] (earlier meth- ods used less sophisticated concepts [6]). These approaches do not consider physical parameters of defects correspond- ing to small-delay faults. On the other hand, interconnect- open simulators concentrate on full-open defects which are detectable by stuck-at and transition fault testing [7, 8, 9]. In this paper, we present a small-delay fault simulation approach which calculates realistic coverage of such faults based on the occurrence probability of the low-resistance in- terconnect open defects. We concentrate on faults with size less than one clock cycle because faults with larger sizes are targeted by stuck-at and transition fault test sets. We first cal- culate, in a manner similar to [4, 5], the fault sizes which are covered by the given test set. Then, we compute the range of resistances of interconnect open defects which would lead to delay faults of size determined in the first step. Finally, we obtain the realistic fault coverage as the probability that the resistance of an actual open defect indeed falls in that range of resistances. The remainder of the paper is structured as follows. A detailed overview of the method is given in Section 2. Fault simulation in the timing domain is explained in detail in Sec- tion 3. The description is enhanced compared with [5] and provides a comprehensive coverage of all stages of the sim- ulation process. The mapping between the size of a delay fault and the resistance of the corresponding interconnect open defect is outlined in Section 4. Experimental results are reported in Section 5. Section 6 concludes the paper. 2 Overview of the Method The inputs of the method are a circuit (a gate-level net-list ac- companied by timing and physical information such as gate delays, clock cycle, transistor and topological parameters), a set of test pairs and a list of faults. Faults are specified by a line (i.e., a gate output) on which a transition is slowed down and the direction of the transition. In case of fanouts, we currently consider faults located at the fanout stem. The exact amount δ of the slowdown (the size of the fault) is not specified in the fault list—indeed, the ranges of δ for which a given fault is detected are an (intermediate) result of the simulation. Furthermore, the probability distribution den- sity ρ of interconnect open defect resistance obtained from manufacturing data is required. Refer to [2] for details on estimating ρ and a typical distribution measured at Philips. Based on this information, the simulator calculates a realis- tic coverage of delay defects with size less than one clock cycle. Figure 1 shows the flow of the simulator in graph form. First, a line-delay fault simulation is performed for each test pair and each fault. The implemented algorithm is a slight extension of that in [5]. For every fault f i and every test pair tp j , the detection interval (in time domain) D t (f i , tp j ) is calculated. The detection interval contains all the values of δ(f i ), the size of fault f i , for which the circuit will fail under test pair tp j , i.e., a transition at one or more outputs will be delayed beyond the clock cycle time. Detection intervals are often of shape [δ min , ∞] for some value δ min . Such a delay range may be transformed into a range of resistances of an open defect [R min op , ∞]. The