A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder Wei-Li Su and Herming Chiueh System-on-Chip Design Lab, Department of Communication Engineering, College of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan. pippenbasket@yahoo.com.tw, chiueh@ieee.org Po-Tsang Huang and Wei Hwnag Low Power System-on-Chip Lab, Department of Electrical Engineering & Institute of Electronic, Microelectronics and Information Systems Research Center, National Chiao Tung University, Hsinchu 300, Taiwan. bug.ee91g@nctu.edu.tw, Hwang@mail.nctu.edu.tw Abstract—A low power pulsed edge-triggered latch based on the static edge-triggered latch (ETL) is presented for survivor memory (SMU) unit of Viterbi decoder for low power high speed wireless local area network (WLAN) applications. By reducing clock loading and transistor number, the proposed low swing static ETL has less clock loading, smaller cell area and power-delay product compared to traditional master-slave register. Moreover, a stage-reduced SMU is introduced later for saving both area and power consumption. The proposed low swing static ETL and stage-reduced SMU are designed and simulated in TSMC 0.13um standard CMOS process, and the operating clock frequency is at 1GHz. I. INTRODUCTION In modern digital communication systems, information is required to be transmitted at high data rates especially in wireless local area network (WLAN) [1]. It will result in increasing power dissipation and system complexity. Besides, for enhancing system performance, an efficient error-control code is often employed. Convolutional codes have been exploited widely in communication systems, which provide a superior error correction capacity while maintaining a reasonable coding complexity. Viterbi algorithm is one of the optimal solutions for decoding convolutional codes with the modest computing resource [2-3]. However, as the requirement of high transmission rate increasing power dissipation of the system, the error-control mechanism also becomes an additional part of power dissipation in system implementation. In modern digital communication very large-scale integration (VLSI) design, power dissipation issue has become more important than the past because of two reasons: one is the limited battery life of portable mobile systems and the other is the high cost of packaging and cooling requirement for reliability in deep submicron technology. These phenomena suggest us to build systems with low power feature [4]. The Viterbi decoder is constructed from three major units [5]: transition metric unit (TMU), add-compare-select unit (ACSU), and survivor memory unit (SMU) as illustrated in Fig. 1. Figure 1. Block diagram of Viterbi decoder. TMU calculates the transition metrics (TM) from the input data. ACSU accumulates transition metrics recursively as path metrics (PM), and makes decisions to select the most likely state transition sequence. Finally, SMU traces the decisions to extract this sequence. There are two main different ways to build SMU: traceback and register- exchange [6]. The former is built of embedded memory element such as static random-access memory (SRAM), and the later is composed of many registers and multiplexers. The traceback approach is a power efficient solution, but not suitable for high speed application because of the limited bandwidth in embedded memory [7]. The register-exchange approach is more direct and intuitional to trace the most likely state transition sequence and easier to operate at higher speed. But its power consumption is proportional to its size and will increase as data throughput increasing. In [8], the SMU’s area of Viterbi accelerator is about 73% of whole chip in physical dimension. Therefore, it is meaning to make improvement for SMU of Viterbi decoder. In this paper, a low power pulsed edge-triggered latch is proposed for low power high speed SMU of Viterbi decoder. Section II introduces relative low power register designs. The architecture of the proposed stage-reduced SMU and proposed low power pulse edge-triggered latch will be discussed in Section III, and here the design concept of low power SMU will be pointed out. The simulation results of low power pulsed edge-triggered latch and the SMU are presented in Section IV. The conclusion and future work is given in Section V. This research was supported by National Science Council, Taiwan (contract numbers: NSC 94-2220-E-009-016ʿ NSC 95ˀ2220-E-009-016) and Ministry of Education, Taiwan (MoE ATU program). The authors would also like to acknowledge the design parameters provided by NCTU- TSMC joined project. 1-4244-0395-2/06/$20.00 ©2006 IEEE. 553