            Renaud Vayrette 1,2,a , Christian Rivero 2,b , Sylvain Blayac 1,c , Karim Inal 1,d 1 STMicroelectronics, Zone industrielle de Rousset, 13106 Rousset cedex, France 2 Centre de Microélectronique de Provence, Ecole Nationale des Mines de Saint-Etienne, 880 route de Mimet, 13541 Gardanne cedex, France a vayrette@emse.fr, b christian.rivero@st.com, c blayac@emse.fr, d inal@emse.fr  copper, thin films, residual stress, microstructure, thickness effect. Abstract. In this work, coupled effects of thickness and annealing temperature on both microstructure and residual stress of electroplated copper thin films are studied. Microstructure is investigated by Electron Backscattered Diffraction (EBSD) and residual stress is estimated from samples curvature. All films exhibit highly twinned grains. Except for several microns films, median crystallite size grows with both film thickness and annealing temperature. Concerning residual stress, it decreases, first as the increase of film thickness, and secondly as the decrease of annealing temperature. The comparison between experiments and stress models demonstrates that the root mechanisms of residual stress generation change with annealing temperature. As well as annealing temperature, film thickness determines the level of residual stress through control of microstructure. Furthermore, EBSD investigations confirmed that the relevant microstructural length to define mechanical properties of thin copper films is the median crystallite size. Introduction Copper is used in the microelectronics industry as interconnect material for technology nodes below 180 nanometers. As feature size decreases, copper interconnect residual stress increases [1]. This leads to reliability problems reinforced by the copper elastic anisotropy and the increasing number of interconnect levels required by design laws. On one hand, electromigration and stress migration resistances deteriorate with increasing residual stress. One the other hand, many applications need very thin chips substrate whose shape and so the handling is influenced by interconnect residual stress. Therefore, control of residual stresses into copper interconnects becomes mandatory for the microelectronics industry. In this perspective, the influence of both thickness and annealing temperature on microstructure and residual stresses of electroplated copper films are studied. Based on knowledge of microstructure, experimental data are compared to analytical models and the root mechanisms of residual stress generation are discussed. Experimental The samples are elaborated on 200 mm diameter silicon wafers on which was grown a 70 Å thick thermal oxide. First, a 250 Å TaN/Ta diffusion barrier and a 1200 Å seed copper layer are deposited by Physical Vapor Deposition (PVD). Then, copper films of different thicknesses are electroplated using a Novellus Sabre equipment with a current density of 15 mA.cm -2 . Finally, samples are directly annealed at 150 and 400°C during 20 min in a N 2 ambient. The heating and cooling rates employed are 8 °C.min -1 . Films thicknesses are determined by sum of PVD and electroplated copper films thicknesses. They are 0.4, 0.7, 1.1 and 5.6 µm. The microstructure of the films is investigated by EBSD in a Field Emission Gun Scanning Electron Microscope Zeiss Ultra 55 (FEG-SEM) with an accelerating voltage of 15 kV. The samples are tilted to 70 ° and the working distance is 15 mm. The lower sample scanned area is 70*70 µm 2 with a step analysis of 0.1 µm. Kikuchi’s bands are collected with Oxford Instruments Materials Science Forum Vol. 681 (2011) pp 139-144 Online available since 2011/Mar/28 at www.scientific.net © (2011) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/MSF.681.139 All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of TTP, www.ttp.net. (ID: 90.80.39.42-13/06/11,09:21:07)