IMPROVING EXTERNAL MEMORY ACCESS FOR AVALON SYSTEMS ON PROGRAMMABLE CHIPS. Hendrik Eeckhaut, Mark Christiaens, Phillipe Faes, Dirk Stroobandt Parallel Information Systems ELIS, Ghent University Sint-Pietersnieuwstraat 41, 9000 Ghent, Belgium email: Hendrik.Eeckhaut@elis.UGent.be ABSTRACT In this paper we present a new hardware design pattern for improving memory transfers to external dynamic memory in Altera’s SOPC-builder tool by reusing the standard DMA IP core for all bulk memory transfers without the need for a CPU. The presented approach doubles the data throughput without the need for extra system resources. In addition it is more effective for choosing optimal clock settings for the different components of the system on a programmable chip. The benefits and limitations of this new approach are illus- trated with a real world example: a bitplane assembler for scalable wavelet based video. The new design is 2.3 times faster with the same clock settings as the original design and uses about 100 logic elements less. Applying our new ap- proach also has a positive impact on energy consumption. 1. INTRODUCTION To be competitive in todays market, electronics products be- came very complex, leading to the implementation of entire Systems-on-a-Chip (SoC). Yet, overwhelming pressure ex- ists for designers to reduce development time and costs. A high level of design reuse among design groups is needed to attain the high productivity rates in SoC design. To effi- ciently reuse IP, a solid integration platform is vital. An inte- gration platform is a SoC design environment that includes architectural specifications and pre-qualified IP blocks de- signed to work together on that platform. For reconfigurable platforms (FPGAs) multiple tools and libraries exist that support designers in system design and integration. Xilinx offers the Xilinx Platform Studio (XPS) for creating custom embedded platforms [1]. XPS is an inte- grated development environment which contains a wide va- riety of embedded tools, IP, libraries and design generators to assist the system designers. Altera offers SOPC-builder to This research is supported by the I.W.T., grant 020174, the F.W.O., grant G.0021.03, the GOA project 12.51B.02 of Ghent University and the Altera university program. automate system integration tasks. Gaisler Research devel- oped GRLIB for system-on-chip development [2]. In con- trast to XPS and SOPC, GRLIB provides a vendor-independent infrastructure for reusable IP cores. In this paper we explore the options of accessing exter- nal dynamic memories in FPGA designs with the SOPC- builder tool. We investigated the different options to opti- mize system bandwidth for custom components. We present a new hardware design pattern to reuse existing IP cores and improve memory transfer efficiency. In Sections 2 and 3 we present SOPC-builder and the standard approach to de- velop custom hardware components. In Section 4 we present our new methodology and we quantify the improvements by building and measuring a real design. We conclude this pa- per with a possible third option (Section 6) and the conclu- sions. 2. SOPC/AVALON SOPC Builder [3] is a software tool that enables to rapidly and easily build and evaluate embedded systems on Altera devices. Essentially it is a system-generation tool that lets you define, parameterize, link, and integrate IP cores (such as soft processor, DSP, communication and memory con- troller cores) in the company’s high-density-programmable- logic devices. The tool automatically generates interconnect logic (Avalon system interconnect fabric [4]) in response to the components (or cores) specified by the designer. This reduces the amount of time designers must spend on peri- pheral integration and increases their ability to reuse periph- erals in subsequent designs. The system interconnect fab- ric uses minimal FPGA logic resources to support address decoding, wait-state generation, peripheral address align- ment, interrupt-priority assignment, data path multiplexing and clock domain crossing. Figure 1 illustrates the intercon- nect fabric of an example design. In contrast to a traditional bus in a processor-based sys- tem, which lets only one bus master access the bus at a time, the Avalon system interconnect fabric uses a slave-side ar- 1-4244-1060-6/07/$25.00 ©2007 IEEE. 311