A New Compact Analog VLSI Model for Spike Timing Dependent Plasticity Mostafa Rahimi Azghadi, Said Al-Sarawi, Nicolangelo Iannella, and Derek Abbott Centre for Biomedical Engineering and School of Electrical and Electronic Engineering, The University of Adelaide, Adelaide, SA 5005, Australia {mostafa,alsarawi,iannella,dabbott}@eleceng.adelaide.edu.au Abstract—Spike Timing Dependent Plasticity (STDP) is a time- based synaptic plasticity rule that has generated significant interest in the area of neuromorphic engineering and Very Large Scale Integration (VLSI) circuit design. During the last decade, STDP and STDP-like learning mechanisms have shown promising solutions for various real world applications, ranging from pat- tern recognition to robotics. This paper presents a novel analog VLSI model for STDP that possesses advantages compared to previously published VLSI STDP designs. The presented STDP circuit is capable of reproducing the outcomes of several well known experiments using various plasticity rules inducing STDP protocols that utilise pairs, triplets, and quadruplets of spike patterns. When the circuit is compared to state-of-the-art VLSI STDP circuits, it shows a compact and symmetric design that makes the proposed circuit a powerful component for use in designing STDP or time-based Hebbian learning experiments and applications. I. I NTRODUCTION Neuromorphic VLSI is the realm of design and implementa- tion of phenomenological and biophysical models of neurons and synapses. It dates back to the early 90’s with early research pioneered by Carver Mead [1]. Ever since, many neuromor- phic engineers have been attempting to implement neurons and synapses in VLSI with various degrees of details and levels of abstraction aimed at benefiting from the low power and compact implementations offered by VLSI technology. There are many examples of VLSI neurons and synapses in the literature [2]–[6]. Neurons are the producers of action potentials (spikes), and synapses are the interfacing elements among neurons, believed to be where learning and memory takes place in the brain. When implementing a synapse within a larger system, such as a network, one should implement the mechanism under which the synaptic efficacy can be altered by pre-synaptic and post-synaptic activities, also referred to as the synaptic plasticity rule [7]. This is in order to ensure that the strength of a synapse can adjust to changes in response to these activities, thus allowing the system to adapt to a dynamic environment [8]. In the past, there have been various rules presented that modify the synaptic weights in response to dif- ferent parameters including but not limited to, i) the activity of pre- and post-synaptic neurons [7], ii) the timing of the spikes from pre- and post-synaptic neurons [9], iii) the membrane potential of the post-synaptic neuron [10], or iv) a cooperative and simultaneous interaction of parameters mentioned in (i) to (iii) [11]. Various VLSI implementations of these rules exist in the literature [5], [12]. In these implementations, the main goal has been to reproduce the results of neurophysiological experiments but, simultaneously, there has always been effort aimed at reducing the area occupied by these learning circuits and/or minimising their power consumption. This paper presents a novel analog VLSI circuit model for triplet-based STDP (TSTDP). The new design presents a significant improvement in terms of physical implementation area and less power compared to previous implementations presented in [2], [5], [6], [12]–[14] without compromising the output response performance when compared to biological ex- periments. More details on how we achieve this improvement is presented in Section III. The circuits are also compared in the discussion and comparison section of the paper. II. PREVIOUS PAIR AND TRIPLET SPIKE TIMING DEPENDENT PLASTICITY CIRCUITS A. Pair-based STDP Circuits Pair-based STDP is the conventional form of a synaptic plasticity rule that potentiates the synaptic efficacy of a synapse, if a pre-synaptic spike precedes the post-synaptic action potential. In contrast, synaptic depression occurs when the order of spikes is reversed, namely if a post-synaptic neuron fires a spike before its pre-synaptic afferent [15]. A well-known phenomenological representation of the PSTDP that implements the above mentioned mechanism is shown in Eq. 1, Δw =  Δw + = A + e ( -Δt τ + ) if Δt ≥ 0 Δw - = -A - e ( Δt τ - ) if Δt< 0 , (1) where Δt = t post - t pre is the time difference between a single pair of post- and pre-synaptic spikes, τ + and τ - are time constants of the learning window, and A + and A - represent the maximal weight changes for potentiation and depression, respectively [16]. From a circuit designer point of view, one can represent the synaptic weight (w) with a voltage stored across a capacitor and hence implement the changes in synaptic weight (Δw) with charging and discharging the capacitor. The amount of the charging and discharging that represents the required potentiation and depression of the synaptic weight can be con- trolled using circuitry that respectively determine the amount of current flowing in and out of the capacitor.   ,((( Proceedings of 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) 7