IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 7, JULY 2009 2019 An 8-Bit Flash Analog-to-Digital Converter in Standard CMOS Technology Functional From 4.2 K to 300 K Ybe Creten, Member, IEEE, Patrick Merken, Willy Sansen, Life Fellow, IEEE, Robert P. Mertens, Fellow, IEEE, and Chris Van Hoof, Member, IEEE Abstract—This paper presents the first Flash analog-to-digital converter (ADC) in standard CMOS technology that functions from 300 K (room temperature) down to 4.2 K. It has been de- signed to operate in cryogenic sensor systems as they are cooled from room temperature to their final cryogenic operating tem- perature. In order to preserve the circuit’s performance over this wide temperature range, even in the presence of tempera- ture-induced transistor anomalies, dedicated architecture and switching schemes are employed. SPICE models for adequate circuit simulation at 4.2 K have been extracted. A first prototype of the chosen architecture, an 8-bit ADC in a standard 0.7 m CMOS technology, achieves a differential nonlinearity (DNL) of 0.5 LSB at room temperature and 1 LSB at 4.2 K at a sampling frequency of 12.5 kHz. Index Terms—Cryogenic ADC, cryogenic CMOS, cryogenic electronics, LHT, low-temperature electronics. I. INTRODUCTION T O OBTAIN the high sensitivity and low leakage cur- rents required by sensor arrays for space-borne imaging systems, particle experiments and superconductor research, deep cryogenic cooling, i.e., cooling down to sub-Kelvin tem- peratures, is essential. Front-end amplifiers, mostly JFET- or CMOS-based single-ended pre-amplifiers and analog multi- plexers, are located in close proximity to these sensor arrays [1]. To avoid large thermal gradients, they also need to be cooled to cryogenic temperatures, which can be as low as 4.2 K, the boiling point of liquid helium (LHT). The analog output signal of the cryogenic front-end is then transported to the so-called “warm electronics”, i.e., electronics working at room temperature (RT), where the data is digitized and processed. For thermal insulation reasons, the distance be- tween the cold electronics and the RT electronics can be up to several meters, leaving the analog signal vulnerable to noise and EMI during transport. Having the analog-to-digital conversion take place in the cryogenic part of the system will substantially improve signal integrity. Manuscript received November 07, 2008; revised March 13, 2009. Current version published June 24, 2009. Y. Creten, R. P. Mertens, and C. Van Hoof are with IMEC, 3001 Leuven, Belgium, and also with the K.U.Leuven, ESAT, B-3001 Leuven, Belgium. P. Merken is with IMEC, 3001 Leuven, Belgium, and also with RMA, 1000 Brussel, Belgium. W. Sansen is with the K.U.Leuven, ESAT, B-3001 Leuven, Belgium. Digital Object Identifier 10.1109/JSSC.2009.2021918 Cryogenic ADCs should also be functional at temperatures up to room temperature. Operation over such a wide temper- ature has several advantages. First, it allows screening of the system’s functionality prior to integration and qualification and also during cooling cycles, which improves the production yield of the whole system. Second, it means that the resulting archi- tecture is more flexible, since it can be operated at moderate as well as deep cryogenic temperatures. Most commercial off-the-shelf (COTS) ADCs experience a substantial performance loss at even moderate cryogenic temperatures. An example of this is described in [2] where the LTC1745, a 12-bit CMOS four-stage pipelined ADC is used [3]. At the relatively mild cryogenic temperature of 90 K, this ADC only exhibits 6 to 7 bits of resolution. On the other hand, superconductor-based ADCs, such as a Niobium-based bandpass delta sigma modulator have been re- ported in literature [4]–[6]. Such ADCs are able to handle ex- tremely high sample frequencies ( 100 GHz [5]) at cryogenic temperatures. However, because they are based on superconduc- tors, their maximum operating temperature is limited to about 2/3 of their critical temperature , which for most presently used superconductors lies around 4.2 K. To the best of the authors’ knowledge, only one ADC has been reported [7] that is functional from room temperature down to 4.2 K. This is because most semiconductor circuits suffer from carrier freeze-out effects [8]. Nevertheless, the reported Succes- sive Approximation architecture is not well suited to the readout of large sensor arrays (e.g., space telescopes) as these require high sampling rates. The flash ADC architecture presented in this paper achieves higher sampling rates, thus overcoming this problem. The subject of Section I is an overview of the aberrant be- haviour of MOS transistors at cryogenic temperatures and how this can be modeled. Section II gives an overview of the im- plemented Flash ADC architecture, focusing on the comparator topology. In Section III, the performance of an 8-bit flash ADC at deep cryogenic (in this case 4.2 K) and room temperatures is discussed. Finally, Section IV states the conclusions of this work. II. PART I: CMOS BEHAVIOR AT CRYOGENIC TEMPERATURES MOS transistors seem to benefit from cooling to mild cryo- genic temperatures ( 77 K) due to the decreased leakage, thermal noise and enhanced mobility predicted by the classical equations. Because of the increase of both the carrier mobility 0018-9200/$25.00 © 2009 IEEE Authorized licensed use limited to: Hong Kong Polytechnic University. Downloaded on November 9, 2009 at 21:08 from IEEE Xplore. Restrictions apply.