A Flexible Topology Selection Program as Part of an Analog Synthesis System P. Veselinovic, D. Leenaerts, W. van Bokhoven Eindhoven University of Technology Dept. of Electrical Engineering, EEB P.O.Box 513, 5600 MB Eindhoven The Netherlands F. Leyn, F. Proesmans, G. Gielen, W. Sansen Katholieke Universiteit Leuven Dept. of Electrical Engineering, ESAT-MICAS Kardinaal Mercierlaan 94, B-3001 Heverlee Belgium Abstract The task of a topology selector within an analog synthesis system is to find the best available analog circuit topology out of a library for a given set of input specifications. The pro- posed selection method consists of a combination of two ap- proaches: procedural filtering and rule-based filtering. The procedural filtering consists of two consecutive phases based on boundary checking and interval analysis. Such a combina- tion of different sorts of filtering is a new technique that allows an optimal trade-off between selection accuracy and required selection time. The tool that implements the method is technol- ogy independent and fully open towards newly added design knowledge. 1 Introduction For the synthesis of analog integrated circuits, an hierarchi- cal design strategy is nowadays being used in most programs [1,2]. The design of higher-complexity modules (e.g. A/D con- verters) is translated into the design of smaller lower- complexity circuits (e.g. comparator) and ultimately devices. In between each of the hierarchical levels the design process con- sists of several steps such as topology selection, circuit sizing, layout generation, extraction and verification. Topology selec- tion has been recognized as the first of those consecutive steps. The goal of topology selection is to search through the set of candidate topologies in a library that implements the required circuit behavior and to find the topology that best matches the input performance specifications in the specified technology process. The set of input specifications can be provided either by a human designer who uses such a tool, or can be derived from a synthesis step at a higher hierarchical level in an auto- mated analog synthesis system. The process can be repeated hierarchically in the sense that a topology is built up from lower -level blocks, for each of which later on in the design process again a lower-level topology has to be selected, and so forth. Although topology selection is an inherent part of analog synthesis, many programs published in the literature so far do not cover this problem. Programs that do handle it, such as OPASYN [3], OASYS [4], or the stand-alone tool HECTOR [5], use heuristic rules to decide between the different prede- fined alternatives. The selection between different related to- pologies in [6] has been integrated within the sizing process, by adding binary variables that control the topology configuration This research was part of a project with ESA-ESTEC (No9890/92/NL/GS) as additional optimization variables. However, none of these techniques makes explicit use of quantitative data about the obtainable performance ranges of the different candidate to- pologies to carry out the selection. The use of such information is, however, essential for the selection of a good topology, and the selection of a good topology is as important to obtain a high- quality design solution (for the lowest power and area con- sumption) as the use of (global) optimization when sizing the selected topology afterwards. Our aim is to use quantitative performance space data to select the most promising topology candidate, which will then be sized by a separate sizing tool. The use of performance-space data also reduces the need for CPU-time-expensive redesign iterations - decreases the likeli- hood that a selected topology later on in the design process turns out not to be able to meet the input specifications. This paper introduces a topology selection composed of analytical filtering (based on boundary checking and interval analysis) and rule-based filtering to obtain a flexible program that combines selection precision with short selection time. In section 2, the topology selection program is situated as essential part of an overall analog synthesis system. Section 3 describes the method used for the selection and covers three filter parts. A detailed design example and implementation aspects are discussed in section 4. Conclusions will be drawn in section 5. 2 Topology selection within analog synthesis The topology selection program presented in this paper is an essential part of the analog module synthesis system (Fig.1), that is presently under development [7]. The main tools in the system are the following programs: topology selection, sizing and optimization, verification, and analog layout generation. The key requirements for the system are modularity, openness and flexibility, which means that the tools are independent and exchangeable and interact through a common database under control of a design controller (which manages the design flow), that new design knowledge and new topologies as well as new technology processes can be added easily, and that different design styles are supported. To accomplish this, two libraries are used in the system, namely a technology library and a cell library. Technology in- dependence (e.g. 2.4 cmos and 0.7 cmos) is established by storing files with the actual values for technological process parameters in the technology library. The cell library contains descriptions of all module and circuit topologies that are known to the system and contains all information that is needed to carry out the different synthesis steps. In order to be able to easily add new cells, the topology selection method must be