IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 1, JANUARY 2003 243 Letters__________________________________________________________________________________________ Computing With Phase Locked Loops: Choosing Gains and Delays José Roberto Castilho Piqueira, Fernando Moya Orsatti, and Luiz Henrique Alves Monteiro Abstract—We simulate a four-node fully connected phase-locked loop (PLL) network with an architecture similar to the neural network proposed by Hoppensteadt and Izhikevich, using second-order PLLs. The idea is to complement their work analyzing some engineering questions like: • how the individual gain of the nodes affects the synchronous state of whole network; • how the individual gain of the nodes affects the acquisition time of the whole network; • how close the free-running frequencies of the nodes need to be in order to the network be able to acquire the synchronous state; • how the delays between nodes affect the synchronous state frequency. The computational results show that the Hoppensteadt–Izhikevich network is robust to the variation of these parameters and their effects are described through graphics showing the dependence of the synchronous state fre- quency and acquisition time with gains, free-running frequencies, and de- lays. Index Terms—Acquisition time, free-running frequencies, phase-locked loops (PLLs), synchronism, synchronous state. I. INTRODUCTION Computation using oscillators is starting to become a reality inspired in the oscillatory nature of the biological neurons and their synaptic connections [1], [2]. The idea is based on the fact that life is strongly connected to oscilla- tions at the several levels of organization: population phenomena, phys- iological synchronization, cellular rhythms, and molecular dynamics are ubiquitous in nature [3]–[7]. Thinking about brain information processing, synchronized oscilla- tions are identified through electroencephalography associated to sys- tems as hippocampus, thalamus, cortex, and frontal lobe playing a fun- damental role to the sensory processes [8], [9]. Phase-locking oscillations seem to be involved in the emergence of memory and cognitive capacity, generating complex adaptive behav- iors for brain controlled organisms [10]–[14]. Using phase-locked loop (PLL) models is an interesting way of in- terpreting the conversion of sensory and motor signals to firing rates [15] providing realistic models for pattern recognition in neural net- works based in phase-locked oscillations [16], [17]. In [16], Hoppensteadt and Izhikevich described a neural network built with commercial PLLs LMC568 or LM565 with interesting ex- perimental results related to pattern recognition. In order to implement Manuscript received August 4, 2002; revised September 10, 2002. The work of J. R. C. Piqueira and L. H. A. Monteiro was supported by CNPq. J. R. C. Piqueira and F. M. Orsatti are with the Departamento de Engenharia de Telecomunições e Controle, Escola Politécnica, Universidade de São Paulo, CEP05508–900 Sao Paulo SP, Brazil (e-mail: piqueira@lac.usp.br). L. H. A. Monteiro is with the Departamento de Engenharia de Telecomuni- cações e Controle, Escola Politécnica, Universidade de São Paulo and also with Pós Graduação em Engenharia Elétrica, Universidade Presbiteriana Mackenzie, CEP05508–900 Sao Paulo SP, Brazil. Digital Object Identifier 10.1109/TNN.2002.806633 Fig. 1. Phase-locked loop. the network they considered the theoretical fact expressed in their The- orem 1, stating that a neural network whose nodes are PLL with -close central frequencies and whose synaptic connections are symmetric al- ways captures the synchronous state. In the synchronous state, all the spatial frequency errors vanish and the spatial phase errors remain constant [18] with the phase error pat- tern providing the recognition [16]. But there are some questions that, from the engineering point of view, need to be discussed as the acquisition time for the steady state and the influence of the delays between the nodes. In this work, using the simulation of a fully connected four node network, we study the influence of the gain of the nodes and the delays between nodes in the acquisition time and in the steady-state frequency. In addition, the changes in the acquisition time and in the steady-state frequency due to the dispersion among the free-running frequencies of the nodes are analyzed. We start describing the dynamics of the nodes and how they form a four-node fully connected architecture with the synaptic connections. Then, the computational results are presented, according to the gain of the single nodes. II. SINGLE-NODE DYNAMICS:SECOND-ORDER PLL PLLs are the basic elements in the electronic extraction of clock signals [19]–[22] and in our models they will be the basic nodes for the full-connected network. Second-order PLLs were chosen for the models, in order to avoid the onset of periodic and chaotic attractors for the phase and frequency errors in an autonomous isolated node of the network that can appear by considering PLL with higher order [23]. PLLs are composed by three elements: a phase detector (PD), a low-pass filter (F) and a voltage controlled oscillator (VCO), connected as shown in Fig. 1. Considering that the input signal and the VCO signal are given by one can prove [20]–[22] that the output of the PD, neglecting the double-frequency terms, can be expressed as being proportional to the sine of the phase-error. That is with the constant depending on and and on the construction of the phase detector. 1045-9227/03$17.00 © 2003 IEEE