Timing Improvement by Low-Pass Filtering and Linear Interpolation for the LabPETT Scanner Rejean Fontaine', Fran9ois Lemieux', Nicolas Viscogliosil, Marc-Andre T6trault', Melanie Bergeron2, Joel Riendeaul, Philippe Berard2, Jules Cadorette2, Roger Lecomte2 1Dept. of Electrical Engineering, 2Dept. of NuclearMedicine and Radiobiology, Universite de Sherbrooke, Sherbrooke, QC, Canada Abstract-Digital processing for Positron Emission Tomography (PET) scanners commonly relies on low frequency sampling (<65 MHz) for reducing power consumption. Timestamps must then be interpolated between samples to achieve adequate time resolution for coincidence detection of annihilation radiation. A low-pass filter based interpolation algorithm adding up to 31 samples between original samples was designed to improve both the energy and timing resolution of the LabPE7UM scanner. An energy resolution refinement of 2 bits can be achieved with such a technique. The better estimation of triggering threshold leads to a more accurate timestamp generation. Timestamp accuracy was investigated as a function of trigger level (5-50 % of maximum value). With the trigger threshold set at 20%, coincidence time resolution of -5.0 ns for LYSO-LYSO and 9.6 ns for LGSO-LGSO are obtained. A real time implementation of the algorithm was achieved in a Xilinx FPGA. I. INTRODUCTION pOSITRON emission tomography relies on extracting event characteristics that occurred in the field of view of the scanner, including position, energy and time of radioactive disintegration for image reconstruction purpose [1]. While energy can be easily estimated by measuring the maximum of a shaped signal, time determination may be more challenging with highly pixellated APD-based systems using low-noise integrated circuits and digital signal processing. In order to overcome these problems, the LabPETTM scanner uses two crystals, placed side by side in a phoswich arrangement, coupled to an Avalanche PhotoDiode (APD) and advanced digital signal processing to extract events characteristics [2][3]. The use of off-the-shelf analog-to-digital converters for digitizing event information directly at the output of the Charge Sensitive Preamplifiers (CSP) is another important feature of the LabPETTM [3]. One real challenge with this approach, when one wants to build a complete scanner, is to keep power consumption at a manageable level. For this reason digital PET scanners are currently using "low frequencies" 40-65 Msps ADC [3][4][5]. Such sampling frequencies result in a relatively long time interval of 15-25 ns between each sample. Some timing refinement must then be made in order to obtain acceptable timing resolution < 5 ns even with fast decay time LSO-like crystals (tr - 40 ns). Although digital approaches perform very well for crystal identification in a phoswich arrangement [6][7], even for low energy photons [8], they are facing an undersampling problem for time extraction. Ideally, a sampling rate in the GHz range would be required, which is unthinkable to implement in a full-size scanner due to the excessive power dissipation in a very confined space. SNR of the analog signals at the CSP output, quantization error and ADC clock jitter are also among contributions to loss of time resolution. This paper will focus mainly on the effect of the accuracy of energy determination on the timing resolution. A filtered interpolation algorithm is proposed to improve energy evaluation. Investigations of APD bias and timing discrimination threshold level complete this preliminary study. II. DIGITAL TIMING METHODS Digital methods have already been applied for extracting event information such as crystal identification, energy and time occurrence in high-energy physics and medical imaging [8][9][10][11]. Such methods can be implemented in high performance processors such as Digital Signal Processors (DSP) or Field Programmable Gate Array (FPGA) with great flexibility. In the latter case, fixed point -in contrast to floating point- arithmetic must be used. Unlike floating point calculation, fixed point calculation achieves a lower resolution for a given dynamic range. It is convenient in fixed point arithmetic to limit the dynamic range between -1 and 1 by using Q7, Q15 or Q31 notation [12]. This approach eases algorithmic implementation and accelerates computing. It is also well suited for FPGA implementation. Several techniques such as digital constant fraction discrimination (CFD), model and linear fit, as well as advanced neural network [10] have been proposed so far for digital timing improvement. In such techniques, a coarse timestamp is updated in synchronization with the high precision sampling clock and an algorithm refines timestamp between two clock edges. Among these techniques, many require some signal preprocessing, i.e. baseline restoration, energy or amplitude detection. The baseline restoration consists in evaluating the DC floor value before the event, which is computed by calculating the mean over a few samples before the trigger (fig 1). On the other hand, event energy or amplitude is commonly estimated by evaluating the maximum of signal pulses. The baseline is simply subtracted 1-4244-0867-9/07/$20.00 ©2007 IEEE.