IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 _______________________________________________________________________________________ Volume: 09 Issue: 08 | August-2015, Available @ http://www.ijret.org 438 A HIGH SPEED DYNAMIC RIPPLE CARRY ADDER Y. Anil Kumar 1 , M. Satyanarayana 2 1 Student, Department of ECE, MVGR College of Engineering, India. 2 Associate Professor, Department of ECE, MVGR College of Engineering, India. Abstract Adder, which is one of the basic building blocks of a processor affect the performance of the processor. There are many adder architectures each of them have their own advantage. Ripple Carry Adder (RCA) architecture occupies the minimum area among the other architectures with lesser power dissipation. RCA experiences more delay due to its carry propagation in critical path; apart from the delay it also experiences glitches. Constant delay (CD) logic solves both the delay problems and glitch related problems. CD logic, due to its pre-evaluated characteristics delivers high speed but due its bulkier nature it is used only in the critical path. In this paper two new techniques are presented which modifies the conventional timing block (requires ten transistors) in CD logic and two new timing blocks one with eight transistors and other with nine transistors are developed. The CD logic with the two new timing block is used in critical path of RCA to achieve higher speed performance with lesser area compared to conventional CD logic. The CD logic with 9-transistor timing block achieves 70% and 39% delay reduction compared to Static and Domino logics. It also achieves 21% and 5% reduction in power dissipation and delay. The 8-transistor version also achieves reduction of delay by 65% and 29% compared to Static and dynamic logic. The two versions of timing blocks have their own advantages where 9-transistor version provides high speed and 8- transistor version provides lesser power dissipation. Simulations are carried out in 130 nm at 1V power supply using mentor graphics tools. Key Words: Critical Path, Feed Through Logic, Constant Delay logic, Pre-evaluated logic, and Timing block. --------------------------------------------------------------------***---------------------------------------------------------------------- 1. INTRODUCTION Addition is very crucial to perform fundamental arithmetic operations. It is used extensively in many VLSI designs and is by so far the most frequently used operation in general- purpose system and in application-specific processors. Also, because the operations of subtraction, multiplication, division and address calculation usually rely on the operation of addition, addition is often seen as an indispensable part of the arithmetic unit. It is dubbed the heart of any microprocessor, DSP architecture, and data processing system. The carry propagation from each bit to its higher position results in a substantial delay. So the adder which lies in the critical delay path effectively determines the system’s overall speed. An efficient adder builds an efficient system. This leads to increasing popularity of smaller and more durable mobile computing and communication systems. There are many adder architectures namely the Ripple Carry Adder (RCA), the Carry Look-Ahead Adder (CLA), the Carry Skip Adder (CSK), the Carry Select Adder (CSL), the Carry Save Adder (CSA) and the Conditional Sum Adder (COS). Each architecture has its own advantages. Among all the adder architectures, the RCA occupies the smallest area and offers good performance for random data input. But the delay depends on length of carry propagation path. As the number of inputs increases delay increases linearly. For an n-bit RCA the delay is nT, where T is the delay of a full adder block. The overall performance of an RCA depends on design on Full adder block. 2. FULL ADDER BLOCK There are many full adder (FA) architectures, where the conventional CMOS adder uses 32 transistors, the highest among the adders and least number of transistors required to design a full adder are six. But the CMOS logic and dynamic logic provides less power dissipation. But the dynamic logic suffers from cascading problem. Domino logic overcomes the cascading problem with an extra inverter [3]. The cascading problem in dynamic logic and an extra inverter overhead is compensated by NORA and ZIPPER logic, but NORA logic suffers from charge leakage and ZIPPER logic needs non overlapping clocks that creates area overhead[1-2]. Some other versions of full adders include Complementary pass transistor logic full adder, Transmission gate full adder, 17-transistor full adder, 14- transistor full adder, 10- transistor full adder [5] etc., In this paper a high speed dynamic logic is proposed which is derived from (Constant Delay) CD logic [8]. Before discussing about CD logic, Feed Through Logic (FTL) [4] should be understood. FTL is shown in fig. 1 overcomes the area over head in domino logic and cascading problem in dynamic logic. By removing the footer transistor and placing a pre-discharge transistor parallel to output node, the cascading problem is solved without an extra inverter. But drawback of FTL is higher power dissipation than dynamic and domino logic. This is due to the short circuit path from VDD to Ground when M1 and NMOS pull down network conducts simultaneously. CD logic overcomes the short circuit problem in FTL with the help of an additional timing block. This timing block prevents the pull up transistors and