Impact and damage on deep sub-micron CMOS technology induced by substrate current due to ESD stress Ph. Galy * , S. Dudit, M. Vallet,C. Richier,C. Entringer,F. Jezequel,E. Petit,J. Beltritti STMicroelectronics, 850 rue jean Monnet, 38926 Crolles, France a r t i c l e i n f o Article history: Received 6 July 2009 Available online 11 August 2009 a b s t r a c t The main purpose of this article is to present some silicon signatures induced by electro-static discharge (ESD) stresses and to propose to approach it with 2D and 3D TCAD simulations and under simplifying assumptions. All test chips are stressed by Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM). Moreover each stress is performed on one chip only to avoid cumulative silicon sig- natures. It appears that the substrate current induced by any of these stresses leads to the same damag on silicon. Thus, HBM, MM and CDM have a common failure and silicon signature. Moreover the informa- tion of the Failure Analysis (FA) only cannot provide an exclusive conclusion in term of ESD stress. Also this kind of local stress can be considered as a latent default for the ESD reliability of devices by oxide overstress and/or charge trapping and/or contact impact and/or STI impact. Ó 2009 Elsevier Ltd. All rights reserved. 1. Introduction ESD stresses are more and more aggressive due to the integra- tion scale down of chips [1]. In this paper, we present the main ob- served results on advanced technologies under ESD test. Typically CMOS bulk technology nodes are C90, C65 and C45. Particularly, all parts are stressed by HBM, MM and CDM, respectively. As expected the more complex stress is the CDM one because it impacts the whole chip and not only the first stage of the ESD network protec- tion within the Input/Output ring. Nevertheless,in particular conditions,HBM or MM stresses can lead to a substrate current after protection device. As an example the reverse protection diodes can be implicit and spread in IP a substrate current. Or this condition can be attributed to the complex ESD network (cut number),to the substrate connection in the frame and in the core of the IC. In this context,the investigation is performed through electrical and silicon signature (current leakage,deprocessing, SEM investigation). Moreover,2D and 3D TCAD simulations are powerful tools to analyse such stress effects. Some assumptions are necessary to launch a numerical investigation.Thus, the study is focused on classical silicon equations (Poisson, transport and continuity) and a current generator is used to simulate a stress (Average Current Slope or quasi-static mode ACS). This allows being independent of the aggressor and ofthe environment ofthe stressed device/ block. Another assumption is to consider that the failure is not attributed to a self heating within the structure but to a current flow and/or parasitic voltage drop. In this condition the thermal equation is not used.The boundary conditions are Dirichlet and Neumann; the mesh structures are compliant with the topologies under study. At the end, comparisons between physical extractions provided by 2D and 3D simulations and SEM views will be shown and discussed. 2. Facilities and tools 2.1.ESD stress and silicon signature detection HBM as well as MM stresses were applied using either a PARA- GON or MK2 tester, according to JEDEC (EIA/JESD22-A114 for HBM, EIA/JESD22-A115 for MM) or ESDA standards (ESD_STM5.1 for HBM or ESD_STM5.2 for MM). CDM stresses were applied by an ORION tester,using Field induced method ESDA standard (ESD Association STM5.3.1) As a failure criteria, we consider any leakage increase above 100 nA on three states I/O or input as well as all degradations in the leakage current on power pads. 2.2.Silicon signature analysis After each electrical stress, a failure analysis was performed to correlate the applied stress with the silicon signature. The typical flow was an HF deprocessing down to silicon with a fine control on the chemical etching time (the goal was not to perform an over etch with wet etch).A typical SEM inspection at low voltage re- vealed some typicalsilicon signatures on the analysed dice. The 0026-2714/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2009.07.039 * Corresponding author.Tel.: +33 4 76 92 55 12. E-mail address: philippe.galy@st.com (Ph. Galy). Microelectronics Reliability 49 (2009) 1107–1110 Contents lists available at ScienceDirect Microelectronics Reliability j o u r n a l homepage: w w w . e l s e v i e r . c o m / l o c a t e / m i c r o r e l