0741-3106 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LED.2015.2411289, IEEE Electron Device Letters > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Abstract— In this work, we demonstrate the existence of the source-drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on Y-function, enabling a precise determination of the various variability sources in advanced FD-SOI MOS devices. Index Terms— Static mismatch variability, matching, Y- function, characterization, CMOS. I. INTRODUCTION rain current variability is one of the most critical issues while scaling down the CMOS devices. It has been recognized since the beginning of mismatch studies that the threshold voltage V th and the current gain factor  local fluctuations are the major sources of drain current I d variability [1,2], both impacting analog and logic circuits like SRAM cells. The advent of ultra-thin body technologies such as Fully Depleted SOI or FinFET has seriously improved the V th variability [3,4], but it has raised new challenges related to the influence of source-drain (SD) series resistance R sd and its variability [5]. In this work, we propose a new methodology for the drain current mismatch study, enabling a precise determination of the various variability sources in advanced FD-SOI MOS devices. In particular, we demonstrate, for the first time, that the source-drain series resistance mismatch is observable in FD-SOI n-MOSFETs, and compare its impact on drain current variability with that of mismatch in other transistor parameters. II. DEVICES AND MEASUREMENT SETUP Electrical measurements were performed on n-MOS transistors issued from an advanced FD-SOI CMOS Manuscript submitted on xxxx. This work was supported in part by the Places2Be ENIAC project and NANO2017 program. E. G. Ioannidis , C. G. Theodorou and G. Ghibaudo are with IMEP- LAHC, MINATEC, Grenoble, BP257, FRANCE (e-mail: ioannidis1980@gmail.com, christoforos.theodorou@imep.grenoble-inp.fr, ghibaudo@minatec.inpg.fr). C. A. Dimitriadis is with Department of Physics, Aristotle University of Thessaloniki, Thessaloniki, 54124, GREECE (e-mail: cdimitri@physics.auth.gr). S. Haendler and E. Josse are with STMicroelectronics, BP16, 38921, Crolles, FRANCE(e-mail: sebastien.haendler@st.com, emmanuel.josse@st.com). technology. The gate stack consists of TiN/Hf-based oxide dielectric with equivalent oxide thickness 1.2nm. The minimum channel length (L) is 20nm. Static measurements of the drain current I d were performed on paired transistors as function of gate voltage V g , in linear region with Agilent B1500/1530 Semiconductor Device Analyzer. The two MOSFETs of the paired test structure are spaced by the minimum allowed distance, placed in identical environment and electrically independent with symmetric connections. The drain voltage was 50mV and the back gate was grounded. In order to study the static variability of the MOS transistor response, we repeated the drain current measurements of the paired transistors to full wafer. III. EXPERIMENTAL RESULTS The drain current mismatch ΔI d /I d for the transistor pair is normally calculated from the linear difference of the two drain current values of the pair (I d2 -I d1 )/I d1 . However, the use of the standard linear difference of current could lead to not meaningful results when I d2 /I d1 becomes very small or very large, artificially saturating to one or zero, respectively. For this reason, in this work we propose to evaluate the drain current mismatch from the logarithmic difference of the two drain current values. Therefore, keeping the same notation for simplicity, we define the drain current mismatch as:             d d d d I I ln I I (1) Indeed, for small change of the two currents, the logarithmic ratio of Eq. (1) reduces to the usual linear difference since ln(I d2 /I d1 )  (I d2 -I d1 )/I d1 , which is conventionally used in matching analysis. Fig. 1 shows typical ΔI d /I d (V g ) characteristics obtained on a large number of transistor pairs for small (a) and large (b) area devices. As can be seen in Fig. 1(a), ΔI d /I d as defined in (1) can reach values up to 2 below threshold (here V th  0.3 V), indicating that the current ratio difference could attain a value almost one decade in weak inversion for small area devices. Interestingly, it should be noted that in large area devices [see Fig. 1(b)], there are cases where ΔI d /I d is larger above threshold, revealing a noticeable difference in ΔI d /I d (V g ) behavior. Note that the strong dispersion of the drain current mismatch at strong inversion has been observed also in other SOI technologies (not presented). This confirms that the behavior of Fig. 1(b) is not specific to a particular lot, but it is characteristic of advanced SOI technologies. As will be shown Impact of source-drain series resistance on drain current mismatch in advanced Fully Depleted SOI n- MOSFETs E. G. Ioannidis, C. G. Theodorou, S. Haendler, E. Josse, C. A. Dimitriadis, Member, IEEE and G. Ghibaudo, Fellow, IEEE. D